A quantum dot has a fluorescent crystalline nanoparticle, wherein the quantum dot has a core-shell structure including a core particle containing a first metal element and a shell layer containing a second metal element, at an interface between the core particle and the shell layer, a third metal element different from the first metal element and the second metal element is present, and an amount of the third metal element with respect to an amount of the first metal element contained in the core particle is 10% or less in terms of molar ratio. As a result the quantum dot has excellent controllability of the emission wavelength and high luminous properties and luminous efficiency.

The present invention relates to a process for preparation of copper fungicide compounds. More particularly, the present invention relates to a continuous process for production of tribasic copper sulphate (TBCS).

The disclosure provides a method of producing a metal compound. The method comprises contacting a metal source with a reaction mixture, wherein the reaction mixture comprises an ionic liquid and an oxidising agent, and thereby producing the metal compound.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A process for producing a process for producing a LnM.sub.2Cu.sub.3O.sub.x high-temperature superconductive powder, the process comprising: i) providing an aqueous solution of Ln, M and Cu and at least one mineral acid; ii) adding at least one sequestrating agent and, optionally, at least one dispersant to the solution to form a precipitate; iii) recovering the precipitate from the solution; and iv) heating the precipitate in a flow of oxygen to form the LnM.sub.2Cu.sub.3O.sub.x powder, wherein Ln is a rare earth element, preferably Y, Ce, Dy, Er, Gd, La, Nd, Pr, Sm, Sc, Yb, or a mixture of two or more thereof, and wherein M is selected from Ca, Sr, and Ba.

An oxide superconducting thin film material includes: a metal substrate having a surface with a biaxially oriented crystal orientation structure; an intermediate layer biaxially oriented and formed on the metal substrate; and an oxide superconducting thin film formed on the intermediate layer and composed of a RE123-based oxide superconductor represented by REBa.sub.2Cu.sub.3O.sub.y. The oxide superconducting thin film includes Br (bromine).

An oxide superconducting thin film material includes: a metal substrate having a surface with a biaxially oriented crystal orientation structure; an intermediate layer biaxially oriented and formed on the metal substrate; and an oxide superconducting thin film formed on the intermediate layer and composed of a RE123-based oxide superconductor represented by REBa.sub.2Cu.sub.3O.sub.y. The oxide superconducting thin film includes Br (bromine).

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.

A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.