Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or dishing of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

Embodiments of the subject application provide a polishing composition for a magnetic disk substrate, whereby the polishing composition contains colloidal silica, at least one of a phosphorus-containing inorganic acid and an organic acid, and water. According to at least one embodiment, the colloidal silica in the polishing composition has an average particle diameter (D50) in the range of 5 to 50 nm observed by a transmission electron microscope. In measuring a volume-based particle size distribution of the colloidal silica by dynamic light scattering, when the particle size distribution is measured by adjusting a concentration of colloidal silica particles to be 0.25 mass %, the colloidal silica contains 10 vol % or less of colloidal silica particles larger than 50 nm. According to at least one embodiment, the polishing composition has 1 to 50 mass % of the colloidal silica, and the polishing composition has the pH (25 C.) in the range of 0.1 to 4.0.

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

Methods, systems, and devices for memory arrays that use a conductive hard mask during formation and, in some cases, operation are described. A hard mask may be used to define features or components during the numerous material formation and removal steps used to create memory cells within a memory array. The hard mask may be an electrically conductive material, some or all of which may be retained during formation. A conductive line may be connected to each memory cell, and because the hard mask used in forming the cell may be conductive, the cell may be operable even if portions of the hard mask remain after formation.

A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A hole portion is formed in the first sacrificial film. A second sacrificial film is formed in the hole portion. A second processed layer is formed above the first sacrificial film and the second sacrificial film, and a second hole is formed in the second processed layer to expose the second sacrificial film. A third sacrificial film is formed on an inner side surface of the second hole, and a fourth sacrificial film is formed on the third sacrificial film. The second sacrificial film is etched using the fourth sacrificial film as a mask. The third sacrificial film exposed by etching the second sacrificial film is etched. The second processed layer is etched using the third sacrificial film as a mask.

The present invention relates to a polishing composition used in application in which a polishing object having a cobalt element-containing layer is polished, including: a cobalt dissolution inhibitor; and a pH adjusting agent, wherein the polishing composition has a pH of 4 or more and 12 or less, and the cobalt dissolution inhibitor is at least one member selected from the group consisting of an organic compound having an ether bond, an organic compound having a hydroxyl group, an organic compound having a carboxyl group and having a molecular weight of 130 or more, and salts thereof. According to the present invention, there is provided a polishing composition capable of suppressing the dissolution of a cobalt element-containing layer when a polishing object having a cobalt element-containing layer is polished.

The present invention relates to a polishing composition used in application in which a polishing object having a cobalt element-containing layer is polished, including: a cobalt dissolution inhibitor; and a pH adjusting agent, wherein the polishing composition has a pH of 4 or more and 12 or less, and the cobalt dissolution inhibitor is at least one member selected from the group consisting of an organic compound having an ether bond, an organic compound having a hydroxyl group, an organic compound having a carboxyl group and having a molecular weight of 130 or more, and salts thereof. According to the present invention, there is provided a polishing composition capable of suppressing the dissolution of a cobalt element-containing layer when a polishing object having a cobalt element-containing layer is polished.

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or dishing of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.