Provided is a particulate phosphor including a single crystal having a composition represented by a compositional formula (Y.sub.1-x-y-zLu.sub.xGd.sub.yCe.sub.z).sub.3+aAl.sub.5−aO.sub.12 (0≤x≤0.9994, 0≤y≤0.0669, 0.001≤z≤0.004, −0.016≤a≤0.315) and a particle diameter (D50) of not less than 20 μm. Also provided is a light-emitting device including a phosphor-including member that includes the phosphor and a sealing member including a transparent inorganic material sealing the phosphor or a binder including an inorganic material binding particles of the phosphor, and a light-emitting element that emits a blue light for exciting the phosphor.

A method for grinding a silicon carbide wafer includes the following steps. Firstly, a single crystal is sliced into several wafers, in which each wafer has a silicon-side surface, which is the first surface. The opposite side is a carbon-side surface, which is the second surface. Subsequently, the silicon-side of the wafer is faced down and placed on a grinding stage for performing a first grinding process. It should be noted that a supporting structure exist between the wafer and the grinding stage. The supporting structure can have a concave or a convex framework. After grinding the carbon-side and removing the wafer from the stage, the wafer will appear convex or concave shape on the carbon-side surface. Thereafter, the wafer is flipped upside down and the carbon-side is placed on a flat stage without any supporting structure. Finally, the silicon-side is ground as a second grinding process.

The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

A silicon wafer forming method includes: a block ingot forming step of cutting a silicon ingot to form block ingots; a planarizing step of grinding an end face of the block ingot to planarize the end face; a separation layer forming step of applying a laser beam of such a wavelength as to be transmitted through silicon to the block ingot, with a focal point of the laser beam positioned in the inside of the block ingot at a depth from the end face of the block ingot corresponding to the thickness of the wafer to be formed, to form a separation layer; and a wafer forming step of separating the silicon wafer to be formed from the separation layer.

A diamond crystal substrate has a substrate surface that is one crystal plane among (100), (111), and (110) and that has atomic steps and terraces structure at an off-angle of 7° or less excluding 0°.

A group III nitride single crystal substrate comprises: a first main face; and a first back face opposite to the first main face, wherein an absolute value of a radius of curvature of the first main face of the substrate is 10 m or more; an absolute value of a radius of curvature of a crystal lattice plane at a center of the first main face of the substrate is 10 m or more; and a 1/1000 intensity width of an X-ray rocking curve of a low-incidence-angle face at the center of the first main face of the substrate is 1200 arcsec or less.

A group III nitride single crystal substrate comprises: a first main face; and a first back face opposite to the first main face, wherein an absolute value of a radius of curvature of the first main face of the substrate is 10 m or more; an absolute value of a radius of curvature of a crystal lattice plane at a center of the first main face of the substrate is 10 m or more; and a 1/1000 intensity width of an X-ray rocking curve of a low-incidence-angle face at the center of the first main face of the substrate is 1200 arcsec or less.

A method for manufacturing an ingot block in which an ingot of a silicon single crystal pulled up by a Czochralski process is cut and subjected to outer periphery grinding to manufacture an ingot block of the silicon single crystal, the method including: a step of measuring a radial center position of the ingot at one or more locations along a longitudinal direction of the ingot, a step of setting a reference position at which an offset amount of the measured radial center position of the ingot is equal to or less than a predetermined eccentricity amount, a step of cutting the ingot into the ingot blocks based on the set reference position, and a step of performing outer periphery grinding on each of the cut ingot blocks.

A method for manufacturing an ingot block in which an ingot of a silicon single crystal pulled up by a Czochralski process is cut and subjected to outer periphery grinding to manufacture an ingot block of the silicon single crystal, the method including: a step of measuring a radial center position of the ingot at one or more locations along a longitudinal direction of the ingot, a step of setting a reference position at which an offset amount of the measured radial center position of the ingot is equal to or less than a predetermined eccentricity amount, a step of cutting the ingot into the ingot blocks based on the set reference position, and a step of performing outer periphery grinding on each of the cut ingot blocks.

Reduced and low work function materials capable of optimizing electron emission performance in a range of vacuum and nanoscale electronic devices and processes and a method for reducing work function and producing reduced and low work function materials are described. The reduced and low work function materials advantageously may be made from single crystal materials, preferably metals, and from amorphous materials with optimal thicknesses for the materials. A surface geometry is created that may significantly reduce work function and produce a reduced or low work function for the material. It is anticipated that low and ultra-low work function materials may be produced by the present invention and that these materials will have particular utility in the optimization of electron emissions in a wide range of vacuum microelectronics and other nanoscale electronics and processes.