A circuit includes, in series between a first terminal and a second terminal of application of a power supply voltage, and first and second branches. The first branch includes a first transistor and a first current source coupled to the first transistor. The second branch includes a resistive element, a second transistor coupled to the resistive element and forming a current mirror with the first transistor and a second current source coupled to the second transistor. The resistive element conditions a threshold of detection of a variation of the power supply voltage.

A circuit board testing system includes a testing fixture and a computer system. The testing fixture includes a contact element, a switching circuit, and a data acquisition unit. The contact element is connected with a circuit board. The switching circuit is connected with the contact element. By enabling the switching circuit, the data acquisition unit acquires a real voltage value corresponding to the electronic component. The computer system is connected with the testing fixture for converting the real voltage value into a real resistance value corresponding to the electronic component. According to the real resistance value, the computer system judges whether the electronic component passes the test.

Tamper-respondent assemblies and methods of fabrication are provided which include a tamper-respondent electronic circuit structure. The tamper-respondent electronic circuit structure includes, for instance, a tamper-respondent sensor having at least one flexible layer and paired conductive lines disposed on the at least one flexible layer. The paired conductive lines form, at least in part, at least one tamper-detect network of the tamper-respondent sensor. The tamper-respondent electronic circuit structure further includes monitor circuitry electrically connected to the paired conductive lines to differentially monitor the paired conductive lines for a tamper event. In enhanced embodiments, multiple interconnect vias electrically connect to two or more layers of paired conductive lines and are disposed in an unfolded interconnect area of the tamper-respondent sensor when the sensor is operatively positioned about an electronic component or assembly to be protected.

A probe position inspection apparatus capable of inspecting the position of contact portions of respective probe tips easily and accurately, an apparatus for inspecting a semiconductor device, and a method of inspecting a semiconductor device are provided. The probe position inspection apparatus includes a transparent plate, a camera for taking an image of one surface of the transparent plate, and a pressure passive member covering the other surface of the transparent plate. The tip of a probe for use in evaluation of a semiconductor device is pressed against the other surface of the transparent plate, with the pressure passive member therebetween. The probe position inspection apparatus further includes an image processor for processing the image taken by the camera to detect the position of the probe in the plane of the transparent plate.

Various apparatus and methods associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and methods to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc.).

Various apparatus and methods associated with a compact electronics test system having user programmable device interfaces and on-board functions adapted for use in various environments are provided. Exemplary embodiments can include a variety of apparatuses and methods to realize an advanced field programmable gate array adapted to perform functional tests on digital electronics within an exemplary 48-pin DIP footprint. One aspect of the invention can include a testing device comprised of components to produce a product that is inexpensive and consumable. A small size of an exemplary embodiment of the invention further allows for desirable shielding to be placed around a highly portable and highly programmable and adaptable testing device in order to protect it from external dangers found in harsh environments (e.g., high levels of radiation when operating in space, etc.).

A method and electronic device for identifying when to replace/clean a probe card or socket are provided. The method includes receiving an ID of the probe card or socket from a tag associated with the probe card or socket before performing an insertion on a test system. For the received ID, there is determined a count of insertions performed on the probe card, and an indication to replace/clean the probe card or socket is generated when the count of insertions equals the threshold value.

A method and electronic device for identifying when to replace/clean a probe card or socket are provided. The method includes receiving an ID of the probe card or socket from a tag associated with the probe card or socket before performing an insertion on a test system. For the received ID, there is determined a count of insertions performed on the probe card, and an indication to replace/clean the probe card or socket is generated when the count of insertions equals the threshold value.

In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus includes a housing. The housing includes a lower housing substrate and an upper housing substrate. The lower housing substrate has a plurality of apertures arranged according to a fine pitch, and the upper housing substrate has a plurality of apertures arranged according to a coarse pitch. A plurality of wires passes through the plurality of apertures from the lower housing substrate to the upper housing substrate. Each wire has plated conductive ends emanating from opposing sides of the housing. The plurality of apertures of the lower housing substrate corresponds to the plurality of apertures of the upper housing substrate. The interface apparatus transforms a pattern having a course pitch to a pattern having a fine pitch.

A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.