A dual chipset architecture, a method of operating a scheduler for a dual chipset architecture, and a computer program product for operating a scheduler for a dual chipset architecture. In an embodiment, the dual chipset architecture comprises a high performance processor, a low performance processor, and a scheduler for the processors. The scheduler is provided for determining an expected data traffic flow to the chipset, and for selectively enabling the high and low performance processors, based on this expected data flow, ahead of this expected data flow reaching the chipset. In one embodiment, a specified data traffic indicator is associated with the expected data traffic flow, and the scheduler uses this specified data traffic indicator to determine the expected data traffic flow. In an embodiment, this specified data traffic indicator is a value for a defined window size for the expected data flow.

A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.

A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR in an embodiment is tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. The resulting dynamic power dissipation during test can be considerably less than known BIST designs.

An integrated circuit senses attempts to access security-related data stored in registers connectable into a scan chain when the attempt includes locally and selectively asserting a scan-enable signal at a corresponding branch of the scan-enable tree when the integrated circuit is in a secure functional mode. When such an attempt is detected, the integrated circuit (i) generates a security warning that causes a reset of the security-related data and/or (ii) engages a bypass switch to disconnect the scan chain from the respective output terminal to preclude the security-related data from being shifted out of the IC via the scan chain.

An electrical safety product circuit topology and its equivalent variations for sensing, control, and reporting of household AC wall current, voltage, power, and energy use, and status of its Ground-and-Arc-Fault-Interrupting internal circuit breaker, is presented herein. The architecture includes any choice of telemetry platform, presumes a plurality of its kind join a wireless network with a plurality of other products endowed with the same platform faculty. Topology variations claimed include current and differential current sensing by toroid or other transformer or by Hall semiconductor means, and include fault condition recognition by microprocessor-based algorithms, or by various analog circuit or digital signal processing (DSP) means. Embodiment variations claimed include any modular circuit breaker panel component form factor, any in-wall outlet or switch-box form factor, and any plug-in AC socket module, in-cord module, and outlet strip form factor.

A sensing structure is presented for use in testing integrated circuits on a substrate. The sensing structure includes a probe region corresponding to a conductive region for connecting to the integrated circuit. A first sensing region at least partially surrounds the probe region. A plurality of sensing elements connects in series such that a first of the plurality of sensing elements has two terminals respectively connected to the first sensing region and the probe region. And a second of the plurality of sensing elements has two terminals respectively connected to the probe region and a first reference potential.

The object of the invention is to provide a secure detachable utility monitoring device to be appended to a utility metering apparatus for controlling at least one utility usage consumption. This is achieved thanks to a detachable metering monitoring device to be connected with a utility meter for controlling at least one utility consumption metered by said utility meter comprising: means to acquire a utility consumption value metered by said utility meter, a first memory to store at least a unique identifier ID and a personal key, both pertaining to said device, means to generate a cryptogram from information data comprising at least the utility consumption value, said cryptogram being encrypted with said personal key, means to generate an information message including at least said cryptogram and the unique identifier ID, means to send the information message to a remote management center.

A secure detachable utility monitoring device is disclosed, to be appended to a utility metering apparatus for controlling at least one utility usage consumption. A detachable metering monitoring device of at least one embodiment includes: a usage reading interface to acquire a utility consumption value metered by the utility meter; a first memory to store at least a unique identifier ID and a personal key, both pertaining to the device; a crypto processor to generate a cryptogram from information data comprising at least the utility consumption value, the cryptogram being encrypted with the personal key; a message generator to generate an information message including at least the cryptogram and the unique identifier ID; and a communication network interface including a sending unit to send the information message to a remote management center.

In the present invention, in a coordinate plane that receives an expression according to a first axis indicating a parameter that impacts a basic rate and a second axis indicating a parameter that impacts a metered power rate, a display unit (230) displays an image indicating coordinates indicating the use state of power received from a grid.

In the present invention, in a coordinate plane that receives an expression according to a first axis indicating a parameter that impacts a basic rate and a second axis indicating a parameter that impacts a metered power rate, a display unit (230) displays an image indicating coordinates indicating the use state of power received from a grid.