Patent classifications
G01R31/00
Power management and state detection system
A power distribution system and method can include a controller and a set of power-using devices. Each power-using device in the set can include a sensor configured to measure a parameter and transmit a sensor signal representing the parameter to the controller, and the controller can respond to the transmitted sensor signal.
Circuit carrier for a battery system and battery system
A circuit carrier is configured to be mounted to a battery system. The circuit carrier includes a circuit carrier board having a first region, a second region, and a third region. The first region is configured to receive a shunt resistor, the third region is configured to receive further electronic components, and the first region and the third region being separated from each other by the second region. The second region is a flexible connection between the first region and the third region and includes a spring-like structure formed from the circuit carrier board.
Modular wireless communication device testing system
Arrangements and techniques for testing mobile devices within a test module. The test modules are portable and may be stacked to provide a modular testing system. A pulley system may be used to move an actuator arm horizontally in the X and Y directions. The actuator arm may be moved vertically in the Z direction such that a tip may engage a touchscreen of a mobile device being tested or a user interface element of the mobile device.
Configuring an analog gain for a load test
A device may determine an analog gain for an aggregated analog signal. The aggregated analog signal may be associated with a calibration test to be used to determine a set of calibration parameters for a load test of a base station. The device may determine the set of calibration parameters for the load test based on an outcome of performing a calibration test. The set of calibration parameters may result in a set of digital gains approximately centered in a digital dynamic gain range. The device may perform the load test after determining the analog gain for the analog signal and based on the set of calibration parameters for the load test.
Glitch power analysis and optimization engine
A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin. A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.
Glitch power analysis and optimization engine
A switching activity report of simulated switching activities of a semiconductor circuit is accessed. A plurality of glitch bottleneck ratios corresponding to a plurality of pins in the semiconductor circuit are determined, comprising by: setting an initial bottleneck ratio on a leaf output pin; and backward traversing the semiconductor circuit to determine a plurality of glitch bottleneck ratios of pins in a fan-in cone of the leaf output pin. A plurality of total glitch powers associated with the plurality of pins is determined, a total glitch power of the plurality of total glitch powers being determined based on a glitch bottleneck ratio and a glitch power of a corresponding pin. One or more critical bottleneck pins among the plurality of pins are identified based on the plurality of total glitch powers. One or more gates associated with the one or more critical bottleneck pins are adjusted to reduce corresponding one or more total glitch powers of the one or more gates.
System and method for monitoring the operational status of tools of an agricultural implement utilizing connectivity
A system for monitoring the operational status of ground-engaging tools of an agricultural implement. The system includes a frame and an assembly including an attachment structure configured to be coupled to the frame and a ground-engaging tool. The ground-engaging tool is pivotably coupled to the attachment structure. The system further includes a shear pin at least partially extending through both the attachment structure and ground-engaging tool to prevent pivoting of the ground-engaging tool about the pivot point when the shear pin is in an operable working condition. Additionally, the system includes an electrical connection through one or more components of the assembly or the shear pin and associated with the shear pin. The system further includes a controller electrically coupled to the electrical connection. The controller is configured to determine a change in the working condition of the shear pin based on an electrical property of the electrical connection.
EMC test system and EMC test method using LiFi
An EMC test system (1) and an EMC test method performed in the EMC test system (1) for testing a DUT (6), wherein the EMC test system (1) comprises an EMC test chamber (2), wherein the DUT (6) is positioned in the EMC test chamber (2), at least one measurement equipment (4) positioned in the EMC test chamber (2) and communication means (3) using LiFi for transmitting and receiving measurement data and/or control data by the measurement equipment (4).
System and method for diagnosing stator inter-turn faults in synchronous motors
A system, method, and non-transitory computer readable medium for diagnosing stator inter-turn faults in a Line Start Permanent Magnet Synchronous Motor (LSPMSM) are described. The method of diagnosing stator inter-turn faults in the LSPMSM includes collecting acoustic signals that are generated from a LSPMSM by a communication device, analyzing via singular spectrum analysis (SSA) the collected acoustic signals for fault detection of the stator inter-turn faults, and determining a fault diagnosis for the fault detection by executing a Fast Fourier Transform (FFT).
METHOD OF COMPUTER SIMULATION
A method of computer simulation is for evaluating the immunity characteristics of a device-under-test by use of a transmission line model that models a transmission line connected to the device-under-test. The method includes a characteristic change node at which parameters representing the transmission characteristics of the transmission line change midway.