Electrostatic discharge (ESD) test systems include a FET-based pulse generator using pairs of back-to-back FETs coupled to produce an ESD pulse based on discharging a capacitor that is coupled in series with a device under test (DUT). A number of FETs can be selected based on an intended ESD test voltage magnitude.

A method for testing a mechanical performance of a lithium ion battery electrode based on a nano-indentation technology includes following steps: connecting an assembled lithium ion battery with an electrochemical test device and setting different test working conditions, so that cyclic charge and discharge experiments are performed on the battery to obtain an attenuation curve of a battery capacity; disassembling the battery and taking out the electrode; scraping some powder from a surface of the cyclic electrode plate and an initial uncyclic electrode plate, and laying down the powder in cold mounting molds separately, pouring the cold mounting solution into the molds; taking out the samples from the molds respectively after the liquid is completely cured and cooled; detecting a mechanical performance after polishing the samples surfaces and analyzing the mechanical performance decay rule of the electrodes.

A ground fault detection device compatible with Y capacitors of various capacities without increasing the capacitance of a detection capacitor is provided. The ground fault detection device includes a first detection capacitor that operates as a flying capacitor, a second detection capacitor that operates as a flying capacitor, a control unit measures the charging voltage of the first detection capacitor and the second detection capacitor, a switching unit that switches between a state using a first measurement system in which the first detection capacitor is charged with the high voltage battery and the charging voltage of the first detection capacitor is measured by the control unit, and a state using a second measurement system in which the second detection capacitor is charged with the high voltage battery and the charging voltage of the second detection capacitor is measured by the control unit.

In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

The invention is a cost effective multisite parallel wafer tester that has an array of stationary wafer test sites; a single mobile wafer handling and alignment carriage that holds a wafer handling robot, a wafer rotation pre-alignment assembly, a wafer alignment assembly, a wafer front opening unified pod (FOUP), and a wafer camera assembly; and a robot that moves the wafer handling and alignment carriage to and from each test site. Each test site contains a wafer probe card assembly and a floating chuck. In use, wafers are loaded from a front opening FOUP into a wafer buffer FOUP from which wafers are retrieved by the wafer handling and alignment assembly. The robot positions the wafer handling and alignment carriage and the associated wafer handling robot, the wafer rotation pre-alignment assembly, the wafer alignment assembly, the wafer FOUP, and the wafer camera assembly in front of and inside a given test site and aligns the wafer to be tested with the probe card inside the test site using the floating chuck.

Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

A test assembly for testing an antenna-in-package (AiP) device includes a socket over a circuit board, where the socket includes an opening for receiving the AiP device; a plunger configured to move along sidewalls of the opening, where during testing of the AiP device, the plunger is configured to cause the AiP device to be pressed towards the circuit board such that the AiP device is operatively coupled to the circuit board via input/output connections of the AiP device and of the circuit board; and a loadboard disposed within the socket and between the plunger and the AiP device, where the loadboard includes a coupling structure configured to be electromagnetically coupled to a transmit antenna and to a receive antenna of the AiP device, so that testing signals transmitted by the transmit antenna are conveyed to the receive antenna externally relative to the AiP device through the coupling structure.

The method for measuring of quick changes of low surface conductivity of dielectrics under electromagnetic interference of line voltage is based on a comparison measurement on a voltage divider and synchronisation of measuring pulses with periodic sinusoidal course of interference when voltage with pre-set parameters of square pulse is brought to the tested dielectric surface and potential is sampled in the voltage divider consisting of the measured dielectric surface and a resistor with preselected resistivity in certain time intervals both before application of the measuring pulse and immediately before its end, and then based on a difference between the values measured using a differential amplifier, the value corresponding to that measured without effect of electromagnetic interference 60 Hz is derived and the result is the possibility to measure quick changes of low surface conductivity of dielectric surface.

The equipment for measurement of quick changes of low surface conductivity of dielectrics under electromagnetic interference of line voltage contains the sensing element (1) monitoring electromagnetic interference and the block (2) monitoring electromagnetic interference that is connected to the sensing element, and the comparative block (3) for control of generation of time sequences is connected to the first output from the block (2) and the block (4) for generation of pulses is also connected to the first output from the block (2), and the output of the block (4) are square pulses 1 ms/±5 V, and the first output 10 μs/±5 V and the second output 10 μs/±5 V are connected to inputs of the block (6) of logic elements, and another output of the block (2) monitoring electromagnetic interference is connected to the comparative element (5), the output of which is connected to the fourth input of the block (6) of logic elements, and the first output of the bloc (6) of logic elements is connected through the block (7) for modulation of pulses to the with the output as pulse 0 to 300 mV to the tested surface in the block (8) of the voltage divider surface/divider-resistor where output from this block (8) of the voltage divider surface/resistor-divider is connected through the block (11) of the voltage follower to the divider with very high input impedance to signal inputs of the first sample-and-hold amplifier (9) and of the second sample-and-hold amplifier (10), and the second input for control of sampling of the first sample-and-hold amplifier (9) and the second input for control of sampling of the second sample

Aspects of the subject disclosure may include, for example, a transmission system having a coupling device, a bypass circuit, a memory and a processor. The coupling device can facilitate transmission or reception of electromagnetic waves that propagate along a surface of a transmission medium. The memory can store instructions, which when executed by the processor, causes the processor to perform operations including restarting a timer to prevent the bypass circuit from disabling the transmission or reception of electromagnetic waves by the coupling device. Other embodiments are disclosed.

Aspects of the subject disclosure may include, for example, a transmission system having a coupling device, a bypass circuit, a memory and a processor. The coupling device can facilitate transmission or reception of electromagnetic waves that propagate along a surface of a transmission medium. The memory can store instructions, which when executed by the processor, causes the processor to perform operations including restarting a timer to prevent the bypass circuit from disabling the transmission or reception of electromagnetic waves by the coupling device. Other embodiments are disclosed.