Patent classifications
G01R35/00
LEAKAGE CURRENT DETECTION DEVICE FOR APPLIANCES
A leakage current detection device includes a self-test unit for activating a simulated leakage current signal; a leakage current detection unit for detecting the simulated leakage current signal and the actual leakage current signal, where when at least one of them is present, the leakage current detection unit activates a trigger signal, and when both of them are absent, the leakage current detection unit deactivates the trigger signal; a self-test feedback turnoff unit for detecting the trigger signal, where when the trigger signal is detected, the self-test feedback turnoff unit deactivates the simulated leakage current signal before a predetermined time point; and a power line disconnect unit for detecting the trigger signal after the predetermined time point, and when the trigger signal is detected, it disconnects the power between the power source and the load.
Magnetic Field Sensor With Shared Path Amplifier And Analog-To-Digital-Converter
A magnetic field sensor comprises at least one magnetic field sensing element configured to generate a measured magnetic field signal responsive to an external magnetic field; a diagnostic circuit configured to generate a diagnostic signal, wherein the diagnostic signal is not dependent on a measured magnetic field; a signal path comprising an amplifier and an analog-to-digital converter for processing the measured magnetic field signal to generate a sensor output signal indicative of the external magnetic field during a measured time period and for processing the diagnostic signal during a diagnostic time period; and a switch coupled to receive the measured magnetic field signal and the diagnostic signal and direct the measured magnetic field signal to the signal path during the measured time period and direct the diagnostic signal to the signal path during the diagnostic time period.
Method of calibrating impedance measurements of a battery
A method of calibration is described that simplifies the measurement of battery impedance conducted in-situ while determining battery state-of-health. A single shunt measurement with a known Sum of Sines (SOS) current, at the desired frequency spread and known root mean squared (RMS) current is used to create a calibration archive. A calibration selected from this archive is used to calibrate an impedance measurement made on the battery.
METHOD OF ADJUSTING AN ELECTRICITY METER
A method of adjusting an electricity meter (1), the method comprising the steps of: measuring the frequency of the distribution grid (3); if the difference between the frequency of the distribution grid and a first frequency is less that a first predetermined threshold, adjusting the measurement module (10) by using first calibration parameters that were produced during a stage of calibrating the meter; if the difference between the frequency of the grid and the first frequency is greater than or equal to the first predetermined threshold, calculating second calibration parameters from the first calibration parameters and from adaptation parameters, and adjusting the measurement module (10) by using the second calibration parameters.
SELF-TEST FOR ELECTROSTATIC CHARGE VARIATION SENSORS
The present disclosure is directed to self-tests for electrostatic charge variation sensors. The self-tests ensure an electrostatic charge variation sensor is functioning properly. The self-tests may be performed while an electrostatic charge variation sensor is active and without interruption to the application employing the electrostatic charge variation sensor.
ACCEPTABILITY CHECK METHOD AND CHECK SYSTEM FOR DETECTION TOOLS
The present application discloses an acceptability check method and check system for detection tools. The check method includes: detecting a plurality of wafers using a detection tool to be checked, to obtain first detection data; detecting the plurality of wafers using an existing detection tool, to obtain second detection data; performing data analysis on the first detection data and the second detection data to obtain category classifications corresponding to the first detection data and the second detection data; and determining whether the first detection data corresponding to the category classification is acceptable; wherein the number of wafers detected using the detection tool to be checked and the number of wafers detected using the existing detection tool are the same.
ACCEPTABILITY CHECK METHOD AND CHECK SYSTEM FOR DETECTION TOOLS
The present application discloses an acceptability check method and check system for detection tools. The check method includes: detecting a plurality of wafers using a detection tool to be checked, to obtain first detection data; detecting the plurality of wafers using an existing detection tool, to obtain second detection data; performing data analysis on the first detection data and the second detection data to obtain category classifications corresponding to the first detection data and the second detection data; and determining whether the first detection data corresponding to the category classification is acceptable; wherein the number of wafers detected using the detection tool to be checked and the number of wafers detected using the existing detection tool are the same.
OPERATION CIRCUIT HAVING LOWER CALIBRATION TIME AND CALIBRATION METHOD THEREOF
A calibration method is configured for calibrating an operation circuit which has a variant offset. The operation circuit includes at least one comparator circuit having a first variant offset. The calibration method provides an adjustable offset to calibrate the variant offset. The method includes: resetting an adjustment parameter to an initial value and configuring the operation circuit to a calibration mode; conducting an initial calibration procedure according to a comparison result of the comparator circuit, to decide an operation calibration code having plural bits; configuring the operation circuit to an operation mode; conducting a predetermined operation procedure according to the operation calibration code, wherein the operation calibration code corresponds to the adjustable offset; conducting a less bit number calibration procedure according to the adjustment parameter and a test calibration code to update the adjustment parameter or the operation calibration code; and repeating the above.
Interlock device for high voltage apparatus
Provided is an interlock device for a high voltage apparatus which enables not only the diagnosis of the connected or non-connected state of a connector during normal operation of the interlock device, but also the detection of a failure of the interlock device itself, including a failure of the interlock loop. The device includes an interlock loop 16 annexed to an HV connector 7 for connecting an electric compressor to an HV battery 8, a detecting signal output unit, a first switching element, a controlling voltage switching circuit operable, in a closed state of the interlock loop, to switch a voltage applied to a control electrode of the first switching element according to an output of the detecting signal output unit, a second switching element operable, in an open state of the interlock loop, to apply to the control electrode of the first switching element an output of the controlling voltage switching circuit so as to cause an ON/OFF state of the first switching element to be inverted from when the interlock loop is in the closed state, and a failure diagnosis unit.
METHOD AND APPARATUS FOR DETECTING ERRORS IN A MAGNETIC FIELD SENSOR
A method for use in a sensor includes generating a first signal by a first sensing module in response to a magnetic field associated with a rotating target, generating a base word based on the first signal, the base word including a first base bit that is generated by comparing respective components of the first signal, reversing a respective polarity of the first signal and offsetting the first signal, generating a test word based on the first signal, the test word being generated after the respective polarity of the first signal is reversed and the first signal is offset, the test word including a first test bit that is generated by comparing the respective components of the first signal, and setting a value of an error signal based on whether the test word matches the base word.