A clock generator can include a Fin Field Effect Transistor (FinFET) oscillator and a phased-locked loop (PLL). The FinFET oscillator can generate a FinFET signal. The PLL can generate an output clock signal based on a reference clock signal and the FinFET signal.

Provided is a multiplier-accumulator (MAC) system, circuit, and method. The MAC system includes a MAC circuit, including a plurality of resistors, having respective resistances, a capacitor connected to the plurality of resistors to charge, in response to a plurality of input signals, the capacitor with electric charge, and a time-to-digital converter (TDC) configured to convert information of a charge time of the capacitor, due to the electric charge, into a digital value, wherein the digital value is an accumulation result of the MAC circuit.

The present description concerns a converter comprising: a circuit (C1) supplying a first pulse (P1) determined by an interval between an active edge of a first signal (S1) and an active edge of a second signal (S2); a circuit (INT) which, at each first pulse (P1), integrates the first pulse (P1), a second pulse (P2) starting after the first pulse (P1) in synchronism with a clock signal (clk), and a third pulse (P3) starting after the third pulse (P3) in synchronism with the clock signal (clk); a circuit (C3) sampling over one bit (OUT1) an output signal (RES1) of the integrator circuit (INT) at the beginning of each third pulse (P3); and two circuits (C2, C4) generating, for each first pulse (P1), respectively the corresponding second pulse and the third corresponding pulse based on the first bit (OUT1).

A semiconductor integrated circuit (IC) comprising a time-to-digital converter (TDC) configured to measure an input-to-output delay of an I/O buffer of a pad the IC, the measured delay reflecting a connection impedance of the pad. A circuit in the IC, or a computer in communication with the IC, determines electrical connection integrity of the pad based on the measured delay of the I/O buffer.

A LiDAR system is disclosed that includes a SPAD unit array and J read group (RG) channels. The SPAD unit array is arranged in M rows and N columns of pixel read groups. Each row includes K pixel read groups. Each pixel read group outputs a detection signal in response to a light pulse that is incident on the pixel read group. Each RG channel corresponds to at least one row of pixel read groups and includes L time-to-digital converters that respectively generate timestamp information corresponding to detection event signals of each of L pixel read groups in the at least one row of pixel read groups in which J<M and L≤K. Each RG channel stores the timestamp information in an accumulator bin of a histogram circuit corresponding to a value of the timestamp information using hardwired addressing based on the value of the timestamp information.

A system includes a ring oscillator including an odd number of inverters arranged in a ring. The system also includes a time to digital converter including an odd number of flops, where each of the flops is coupled to an output of a different inverter. The system includes a level shifter coupled to the inverters and to the flops. The system also includes a Gray counter coupled to at least one of the flops. The system includes a decoder coupled to the time to digital converter. The system also includes a phase frequency detector coupled to the decoder.

Aspects of the disclosure provide for an apparatus comprising a time-to-digital converter (TDC) and a processor coupled to the TDC. In some examples, the TDC may be configured to receive a signal and generate a measurement result indicating a time between start and stop events of the signal. The processor may be configured to receive the measurement result, compare the measurement result to a target value, and determine a non-linearity model configured to correct a variance of the measurement result from the target value.

An arousal level prediction apparatus and method are disclosed. The arousal level prediction apparatus obtains first biological information indicating current biological information of the user, obtains first environment information indicating a current environment around the user, and obtains living information of the user indicating an activity history of the user. The arousal level predication apparatus includes a process that calculates a first arousal level indicating a current arousal level of the user based on the first biological information, predicts a second arousal level, which is an arousal level of the user at a certain period of time later, based on the first arousal level, the first environment information and the living information, and outputs the second arousal level.

Various embodiments of the present technology may provide methods and apparatus for a time-to-digital converter. The time-to-digital converter may include a state machine that increments/decrements according to an input signal and a count value. The time-to-digital converter may further include a register to store the count value according to the input signal.

The present disclosure generally relates to techniques and user interfaces for transitioning between a standard display mode and a low power display mode.