A method of operating a fuel injector includes determining a fuel pressure and a total fuel mass M.sub.TF to be injected per combustion cycle, defining first and second pulse widths PW.sub.1 and PW.sub.2 corresponding to first and second commanded fuel masses CM.sub.1 and CM.sub.2 wherein CM.sub.1+CM.sub.2=M.sub.TF, actuating the injector for the first and second pulse widths, detecting an opening delay for the injector, and storing the opening delay. The method may further include increasing PW.sub.1 and decreasing PW.sub.2 by a predetermined amount, repeating selected steps until PW.sub.2 is less than or equal to a predetermined minimum pulse width, changing the fuel pressure by a predetermined pressure amount, cycling through selected steps until the fuel pressure reaches a predetermined target fuel pressure, and commanding the injector to open earlier than a normally commanded opening time by a lead time based on stored opening delay data.

Disclosed are a method for estimating a load current of a power supply, and a USB-type converter. The method includes steps described below. After an input port of a USB connection line is connected to the power supply and an output port of the USB connection line is connected to a load, the power supply supplies power to the load through the USB connection line to obtain an initial load current value; an actual voltage value of the input port is detected, when the actual voltage value of the input port is less than a preset voltage value, the initial load current value is adjusted until the actual voltage value of the input port corresponding to an adjusted load current value is not less than the preset voltage value, and the adjusted load current value is output as a load current value of the power supply.

This disclosure describes techniques for controlling a power supply voltage for a high-side gate driver that is used in a power converter. In some examples, in response to an overvoltage condition that occurs on an input voltage lead of a power converter, a power converter may decouple a terminal of a charge pump capacitor from the input voltage lead, and couple the terminal of the capacitor to a reference voltage lead. In further examples, in response to an overvoltage condition that occurs on an input voltage lead of a power converter, a power converter may turn off both switching transistors.

A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

A voltage charge pump circuit with boost capacitor segments and boost delay chain structures are provided. The voltage charge pump circuit comprising a plurality of boost capacitor segments each of which is individually controlled by a respective signal line of a boost delay chain structure.

Controlling power delivered to a heating device occurs using a phase control, wherein the phase control includes changing a cut-off phase of an alternating current electrical signal delivered to the heating device. The power delivered to the heating device is increased from zero to an operational level using the phase control. The level of the power delivered to the heating device is maintained at the operational level using both the phase control and an integral half cycle control. The integral half cycle includes selectively removing a plurality of half cycles from the alternating current electrical signal delivered to the heating device.

A method of operating a resolver management device according to the present invention includes: generating an excitation signal by using an external control signal; counting a time interval (a first delay time) to a first pole of the excitation signal based on one period of the external control signal by using an internal clock; receiving an excitation signal reflected from a resolver sensor; counting a time interval (a second delay time) to a second pole of the reflected excitation signal at the first pole by using the internal clock; and transmitting a first count value corresponding to the first delay time and a second count value corresponding to the second delay time to a microcontroller unit (MCU).

A method of operating a resolver management device according to the present invention includes: generating an excitation signal by using an external control signal; counting a time interval (a first delay time) to a first pole of the excitation signal based on one period of the external control signal by using an internal clock; receiving an excitation signal reflected from a resolver sensor; counting a time interval (a second delay time) to a second pole of the reflected excitation signal at the first pole by using the internal clock; and transmitting a first count value corresponding to the first delay time and a second count value corresponding to the second delay time to a microcontroller unit (MCU).

An electrical circuit can bias a sensor, measure current from a sensor, or both of these. In some examples, the electrical circuit can include a comparator having two input terminals and an output terminal. The comparator can be configured to compare input signals applied to the two input terminals and generate an output signal at the output terminal based on the comparison. The electrical circuit can include a switch having a control terminal that is electrically coupled to the output terminal of the comparator. The switch can also include a first connection terminal that is electrically coupled to the sensor and a second connection terminal that is electrically coupled to a charge-packet source. The switch can be switchable between (i) an open state to electrically decouple the sensor from the charge-packet source, and (ii) a closed state to electrically couple the sensor to the charge-packet source.

Embodiments are provided for voltage regulators that include a first, a second, a third, and a fourth NMOS transistor cascoded between a high voltage source and a low voltage output; a resistor network including a first, a second, a third, and a fourth resistor connected in series between the high voltage source and ground, wherein gate electrodes of the second, third, and fourth NMOS are respectively connected to nodes between the first and second resistors, the second and third resistors, and the third and fourth resistors; and a multi-stage charge pump configured to provide a first bias voltage to a gate electrode of the first NMOS and a second bias voltage to the gate electrode of the second NMOS.