Patent classifications
G06E3/00
NOISE REDUCED CIRCUITS FOR TRAPPED-ION QUANTUM COMPUTERS
Embodiments described herein are generally related to a method and a system for performing a computation using a hybrid quantum-classical computing system, and, more specifically, to providing an approximate solution to an optimization problem using a hybrid quantum-classical computing system that includes a group of trapped ions. A hybrid quantum-classical computing system that is able to provide a solution to a combinatorial optimization problem may include a classical computer, a system controller, and a quantum processor. The methods and systems described herein include an efficient and noise resilient method for constructing trial states in the quantum processor in solving a problem in a hybrid quantum-classical computing system, which provides improvement over the conventional method for computation in a hybrid quantum-classical computing system.
Optical Signal Processing Device
There is provided an optical signal processing device that generates a mask function in an optical domain to enable high-speed RC processing. For light emitted from a laser light source, an optical modulator modulates at a modulation period at least one of the intensity and phase values of the optical electric field. Thereby, the light emitted from the laser light source becomes an input signal. The input signal is entered into an optical FIR filter unit. For the input signal, the term corresponding to the mask function is multiplied at the optical FIR filter unit and weighted. Thereby, the input signal is converted into an input signal modulated. The modulated input signal enters via an optical coupler, an optical circulation circuit which is loaded with a variable attenuator and a nonlinear response element. The circulating optical signal is branched into two by an optical coupler. One branched light is converted into an intermediate signal at an optical receiver. The intermediate signal is computed by a formula at an electric signal processing circuit, and thereby, the operation as RC can be performed.
Dynamic processing element array expansion
A computer-implemented method includes receiving a neural network model that includes a tensor operation, dividing the tensor operation into a set of sub-operations, and generating instructions for performing a plurality of sub-operations of the set of sub-operations on respective computing engines of a plurality of computing engines on a same integrated circuit device or on different integrated circuit devices. Each sub-operation of the set of sub-operations generates a portion of a final output of the tensor operation. An inference is made based on a result of a sub-operation of the plurality of sub-operations, or based on results of the plurality of sub-operations.
Directional drilling control system and methods
A method for forming a wellbore in an earth formation includes positioning a drill string in a wellbore; the drill string including a bottom hole assembly (BHA) that includes a steering unit, one or more sensors responsive to one or more formation properties, and one or more sensors responsive to the current orientation of the BHA in a wellbore. The method also includes receiving information from the BHA related to the formation properties and information related to a current orientation of the BHA in the wellbore and processing the information using computing device that is either a programmable optical computing device or a quantum computing device. The computing device calculates the position of formation features with respect to current wellbore position in real time and compare the current position to a prescribed path.
Tiny low power current mode analog to digital converters for artificial intelligence
Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and dynamic power consumption.
Method for training and testing data embedding network to generate marked data by integrating original data with mark data, and training device and testing device using the same
A method for learning a data embedding network is provided. The method includes steps of: a learning device acquiring and inputting original training data and mark training data into the data embedding network which integrates them and generates marked training data; inputting the marked training data into a learning network which applies a network operation to them and generates 1-st characteristic information, and inputting the original training data into the learning network which applies a network operation to them and generates 2-nd characteristic information; learning the data embedding network such that a data error is minimized, by referring to part of errors referring to the 1-st and the 2-nd characteristic information and errors referring to task specific outputs and their ground truths, and a marked data score is maximized, and learning a discriminator such that a original data score is maximized and the marked data score is minimized.
ADDRESSING SYSTEM, ADDRESSING APPARATUS AND COMPUTING APPARATUS
An addressing system, an addressing apparatus and a computing apparatus are provided. The addressing system includes a first acousto-optic processing component and a second acousto-optic processing component. The first acousto-optic processing component is used for generating a diffraction beam for an addressing operation in a preset number of dimensions. The second acousto-optic processing component is used for determining emitting directions of the generated diffraction beam in various dimensions, and outputting a diffraction beam according to the determined emitting directions to perform an addressing operation for a qubit array in the preset number of dimensions. A first radio frequency of the diffraction beam generated by the first acousto-optic processing component is used for compensating for a second radio frequency of diffraction beams outputted by the second acousto-optic processing component from different emitting directions.
ADDRESSING SYSTEM, ADDRESSING APPARATUS AND COMPUTING APPARATUS
An addressing system, an addressing apparatus and a computing apparatus are provided. The addressing system includes a first acousto-optic processing component and a second acousto-optic processing component. The first acousto-optic processing component is used for generating a diffraction beam for an addressing operation in a preset number of dimensions. The second acousto-optic processing component is used for determining emitting directions of the generated diffraction beam in various dimensions, and outputting a diffraction beam according to the determined emitting directions to perform an addressing operation for a qubit array in the preset number of dimensions. A first radio frequency of the diffraction beam generated by the first acousto-optic processing component is used for compensating for a second radio frequency of diffraction beams outputted by the second acousto-optic processing component from different emitting directions.
SYSTEM FOR PHOTONIC COMPUTING
A system for photonic computing, preferably including an input module, computation module, and/or control module, wherein the computation module preferably includes one or more filter banks and/or detectors. A photonic filter bank system, preferably including two waveguides and a plurality of optical filters optically coupled to one or more of the waveguides. A method for photonic computing, preferably including controlling a computation module, controlling an input module, and/or receiving outputs from the computation module.
Apparatus and methods for optical neural network
An optical neural network is constructed based on photonic integrated circuits to perform neuromorphic computing. In the optical neural network, matrix multiplication is implemented using one or more optical interference units, which can apply an arbitrary weighting matrix multiplication to an array of input optical signals. Nonlinear activation is realized by an optical nonlinearity unit, which can be based on nonlinear optical effects, such as saturable absorption. These calculations are implemented optically, thereby resulting in high calculation speeds and low power consumption in the optical neural network.