In one embodiment, a method for managing a dynamic total power level for an information handling system includes: identifying, by a power manager of the information handling system, a first power level associated with a processor subsystem of the information handling system, the first power level based on a cooling capacity associated with the information handling system; identifying, by the power manager, a second power level associated with a graphics processing unit of the information handling system, the second power level based on a performance associated with the processor subsystem; determining, by the power manager, the dynamic total power level based on the first power level and the second power level; and modifying, by the power manager, a fixed total power level based on the dynamic total power level, the dynamic total power level causing the processor subsystem and the GPU to operate within the dynamic total power level.

Methods and systems for power management are disclosed. The disclosed power management method and systems may improve the likelihood of data processing systems providing desired computer implemented services while meeting power budget goals and/or other types of goals regarding power consumption, use, and/or provisioning. To improve the likelihood of the power budgets being met, the system may dynamically update power allocations to various components of data processing systems. The power allocations may be dynamically allocated by predicting how changes in existing power allocations may impact the ability of the data processing system to service power allocation requests. If it appears that changes in one or more existing power allocations may allow a power allocation request to be serviced, then the power allocations may be dynamically reallocated to free allocable power. The freed allocable power may be used to service the power allocation.

Provided are a method and a device for determining a clock frequency of a router card. The method includes steps A to D. In step A, a target average port traffic is obtained by using the number of ports and a total to-be-served traffic higher than zero of a target network node for each of neighboring network nodes. In step B, a clock frequency meeting the demand of the target average port traffic is determined as a clock frequency of any router card, the clock frequency of which has not been set, in the target network node. In step C, the total to-be-served traffic and the number of ports are updated. In step D, step A is performed, in a case that there is the updated total to-be-served traffic higher than zero.

On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.

An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset.

An information processing apparatus includes: a communication unit that performs communication with a power supply controller controlling supply and shutoff of power supply of a device; an operation receiving unit that receives input of user operation; an instructing unit that instructs the power supply controller via the communication unit to supply or shut off power supply in response to user operation concerning supply or shutoff of power supply of the device; a setting unit that sets power supply specified to be not permitted to shut off in response to user operation to specify the power supply to be not permitted to shut off; and an instruction disabling unit that disables an instruction to shut off power supply by the instructing unit when the power supply set to be not permitted to shut off is a target of the instruction to shut off power supply by the instructing unit.

A first external tool (10A) serially connected to an electronic controller (20A) through a pair of communication lines (LANH, LANN) applies a high voltage (Vaa) higher than a normal control voltage (Vcc) to the communication line (LANH) when a program is written. The electronic controller (20A) recognizes connection of the first external tool (10A) by a comparison circuit (212A) for monitoring a received voltage and a write-mode determination circuit (218A), initializes a microprocessor (200), and receives and stores an total control program (TCPRG) in a program memory (204A) based on a content of a boot program memory (201). During an operation of the electronic controller (20A), the external tool (10A) is removed and the high voltage (Vaa) is not applied to the communication line (LANH). Therefore, the electronic control apparatus is not erroneously placed in the write mode.

A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.

A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.

A computing device in accordance with an example includes a first operating system and a second operating system. The computing device includes a communication channel to exchange data between the first and second operating systems, and a controller to select one of the first and second operating systems based on a mode of the computing device, where the first and second operating systems are executed substantially in parallel on a processor of the computing device.