A computer-implemented method for performing data storage. The method comprises the steps of: receiving data to be stored from a data source; segmenting the data into immutable core objects each being written into a collection and being assigned a unique object ID; grouping the immutable objects into blobs each including at least one of the objects and being assigned a unique blob ID derived from the object ID of the at least one of the objects included therein, with the last blob of the collection being identifiable as such; defining a state of the collection by linking at least one subset of the core objects of the collection to one another with a last object of each subset being the object head of the corresponding subset and storing identification information of the head object; and storing each one of the blobs onto at least one backend.

To support realization of efficient data conversion processing even between data with undefined conversion definition and the like. A data integration apparatus includes an arithmetic unit that calculates a similarity between a data format of a table regarding predetermined data, data format information of which has not stored in a storage device, and a master data format of each predetermined table, specifies a predetermined table in the master data format having the similarity that satisfies a predetermined criterion, calculates a similarity between the master data format of the specified predetermined table and a data format of each table of each system, specifies a predetermined table of a predetermined system having the similarity that satisfies a predetermined criterion, and outputs conversion processing definition information on the specified predetermined table in the master data format and the specified predetermined table of the predetermined system as reusable conversion processing component candidate information.

A display apparatus, a method for executing an application thereof, an external device remotely controlling the display apparatus, and a method for providing an application control screen thereof are provided. The display apparatus includes a display that displays an application execution screen, the application execution screen displaying an application; a communication unit that communicates with an external server and an external device that remotely controls the display apparatus; and a control unit that transmits to the external device a generation signal that instructs the external device to generate an application control screen in response to receiving an input command to execute the application, controls the communication unit to receive a command from the external device input through the application control screen, and operates the application according to the received command.

Aspects of the subject technology relate to display circuitry such as backlight control circuitry for operating parallel strings of light-emitting diodes (LEDs). A voltage supply circuit of the backlight control circuitry provides a common supply voltage to the strings of LEDs. Headroom control circuitry samples a residual voltage at the end of each string, determines a minimum of the residual voltages, and provides feedback, based on the determined minimum voltage, to the voltage supply circuit. A headroom control feedback loop may be provided including sampling lines coupled to the second end of each string of LEDs for sampling a residual voltage of each string. Headroom control circuitry may modify the supply voltage based on the minimum residual voltage. Sample-and-hold circuitry may be provided that holds the sampled residual voltages until the voltage supply circuit is ready for an update.

Techniques for data manipulation using filling logic for tensor calculation are disclosed. A processor and a memory subsystem for data manipulation are obtained. A FIFO is configured between the processor and the memory subsystem, where the FIFO is coupled with the processor. FIFO filling logic is configured between the FIFO and the memory subsystem, wherein the FIFO filling logic is connected to the FIFO and the memory subsystem. The processor consumes an element stream from the FIFO, wherein the element stream flows to the FIFO from the memory subsystem through the FIFO filling logic. The element stream from the FIFO comprises elements of a tensor, and the consuming comprises performing tensor calculations. An address is provided to the FIFO filling logic for accessing data from the memory subsystem using an address generator.

A display system includes a continuous flexible display, two book halves, two main display supports, and a movement synchronizing coupling. The two book halves is connected to each other via a hinge mechanism. The hinge mechanism has two hinges, and each hinge is rotatable about respective axis. Each of the two main display supports connects to one of the two book halves and is configured to support the flexible display. The coupling is connected to the two main display supports and rotating about a rotation axis that is parallel to the axis of hinge to enable a synchronized movement of the two main display supports.

Embodiments of instructions and methods of execution of said instructions and resources to execute said instructions are detailed. For example, in an embodiment, a processor comprising: decode circuitry to decode an instruction having fields for an opcode, a packed data source operand identifier, and a packed data destination operand identifier; and execution circuitry to execute the decoded instruction to convert a data element from a least significant packed data element position of the identified packed data source operand from a fixed-point representation to a floating point representation, store the floating point representation into a 32-bit least significant packed data element position of the identified packed data destination operand, and zero all remaining packed data elements of the identified packed data destination operand is described.

A device, including a low-ohmic circuit path; a normal operation circuit path coupled in parallel with the low-ohmic circuit path; and a circuit element configured to select between the low-ohmic circuit path and the normal operation circuit path.

A stream of data is accessed from a memory system by an autonomous memory access engine, converted on the fly by the memory access engine, and then presented to a processor for data processing. A portion of a lookup table (LUT) containing converted data elements is preloaded into a lookaside buffer associated with the memory access engine. As the stream of data elements is fetched from the memory system each data element in the stream of data elements is replaced with a respective converted data element obtained from the LUT in the lookaside buffer according to a content of each data element to thereby form a stream of converted data elements. The stream of converted data elements is then propagated from the memory access engine to a data processor.

A computer program product, an apparatus, a functionally safe programmable controller and a method for processing data, wherein an uncoded real number x is converted into a logarithmic number system (LNS) coded integer x.sub.LNS via a predetermined conversion rule for a logarithmic number system (LNS) in accordance with the relationship: x.sub.LNS=sgn(x).Math.2.sup.m+Id|x|.Math.2.sup.n, where sgn(x) denotes a sign function of the uncoded real number x, Id|x| denotes a binary logarithm of the uncoded real number x, m denotes a first exponent and n denotes a second exponent, and the LNS-coded integer x.sub.LNS is coded into an arithmetically coded integer x.sub.c via arithmetic coding such that the required integer operations is reduced.