A computer program product, an apparatus, a functionally safe programmable controller and a method for processing data, wherein an uncoded real number x is converted into a logarithmic number system (LNS) coded integer x.sub.LNS via a predetermined conversion rule for a logarithmic number system (LNS) in accordance with the relationship: x.sub.LNS=sgn(x).Math.2.sup.m+Id|x|.Math.2.sup.n, where sgn(x) denotes a sign function of the uncoded real number x, Id|x| denotes a binary logarithm of the uncoded real number x, m denotes a first exponent and n denotes a second exponent, and the LNS-coded integer x.sub.LNS is coded into an arithmetically coded integer x.sub.c via arithmetic coding such that the required integer operations is reduced.

An Input/Output (I/O) adapter device is provided. The I/O adapter device comprises: a device interface configured to communicate with a first device and a second device communicatively coupled to the I/O adapter device; a host interface configured to support communication with a frontend driver of a host device via a software interface of the host device; a first emulated backend driver configured to communicate with the frontend driver through the host interface using the software interface and to communicate with the first device to provide the frontend driver with access to the first device; and a second emulated backend driver configured to communicate with the frontend driver through the host interface using the software interface and to communicate with the second device to provide the frontend driver with access to the second device.

A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

An embodiment of the present invention is directed to financial transaction ecosystems. A transaction processing ecosystem comprises: a plurality of data sources; a capture interface; and a financial transaction processing system comprising a message bus and a plurality of processors interfacing with the message bus and configured to perform: receiving, via the capture interface, raw data for a payment transaction, wherein the raw data comprises client instructions; normalizing, via the capture interface, the raw data into a normalized transaction format based on a standard data model; publishing, via the capture interface, the normalized transaction format to a message bus; processing, via a first processor of the plurality of processors, the normalized transaction format; and completing the transaction.

A data-brokerage service that facilitates data sharing between Internet-of-Things (IoT) platforms via peer-to-peer connections is described. In various embodiments, the data-brokerage service receives, from an IoT platform acting as data consumer, a selection of data fields included in a plurality of data streams provided from a plurality of respective IoT platforms acting as data producers. Responsive to the selection, the data-brokerage service causes the plurality of data-producer platforms to stream at least the selected data fields of the plurality of data streams to the data-consumer platform, and causes the data-consumer platform to combine the streamed data fields received from the plurality of data-producer platforms into a single target data stream.

A data-brokerage service that facilitates data sharing between Internet-of-Things (IoT) platforms via peer-to-peer connections is described. In various embodiments, the data-brokerage service receives, from an IoT platform acting as data consumer, a selection of data fields included in a plurality of data streams provided from a plurality of respective IoT platforms acting as data producers. Responsive to the selection, the data-brokerage service causes the plurality of data-producer platforms to stream at least the selected data fields of the plurality of data streams to the data-consumer platform, and causes the data-consumer platform to combine the streamed data fields received from the plurality of data-producer platforms into a single target data stream.

A memory arrangement can store a matrix of matrix data elements specified as index-value pairs that indicate row and column indices and associated values. First split-and-merge circuitry is coupled between the memory arrangement and a first set of FIFO buffers for reading the matrix data elements from the memory arrangement and putting the matrix data elements in the first set of FIFO buffers based on column indices. A pairing circuit is configured to read vector data elements, pair the vector data elements with the matrix data elements, and put the paired matrix and vector data elements in a second set of FIFO buffers based on column indices. Second split-and-merge circuitry is configured to read paired matrix and vector data elements from the second set of FIFO buffers and put the paired matrix and vector data elements in a third set of FIFO buffers based on row indices.

A system and method are provided for use with streaming blocks of data, each of the streaming blocks of data including a number bits of data. The system includes a first compressor and a second compressor. The first compressor can receive and store a number n blocks of the streaming blocks of data, can receive and store a block of data to be compressed of the streaming blocks of data, can compress consecutive bits within the block of data to be compressed based on the n blocks of the streaming blocks of data, can output a match descriptor and a literal segment. The match descriptor is based on the compressed consecutive bits. The literal segment is based on a remainder of the number of bits of the data to be compressed not including the consecutive bits. The second compressor can compress the literal segment and can output a compressed data block including the match descriptor and a compressed string of data based on the compressed literal segment.

An embodiment of a semiconductor package apparatus may include technology to load compressed symbols in a data stream into a first content accessible memory, break a serial dependency of the compressed symbols in the compressed data stream, and decode more than one symbol per clock. Other embodiments are disclosed and claimed.