Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Provided is a method of managing a register port, the method including performing scheduling on register ports that are used during a plurality of cycles to enable performing of a calculation; encoding data of the register ports according to results of the scheduling, the encoding of the data including, with respect to data of one of the register ports that does not have a schedule during one of the plurality of cycles, equally encoding the data of the one register port during the one cycle with data of an adjacent cycle of the one register port, the adjacent cycle being adjacent to the one cycle; and transmitting results of the encoding to a device that includes the register ports.

A buffer logic unit of a packet processing device that is configured to allocate single pages to two or more packets if the current packets stored on the page do not fully fill the single page and to store and maintain page slot specific page state data for each of the packet data stored on the pages.

Accessing a circular buffer in memory from a processor may be performed with the aid of precomputed values stored in a pointer descriptor field of a processor storage element, such as a register. The pointer descriptor may store a precomputed value for calculating a memory address in the circular buffer, which may include two values, in which the two values are based, at least in part, on the size of the circular buffer, but neither be the size of the circular buffer. The first value may be used to derive a starting memory location for a circular buffer. The second value may be used in combination with the first value to calculate an end memory location. The start and end locations or addresses, along with the precomputed stored values, are then used to calculate the next address based on the current address of a circular buffer in an efficient manner.

A multi-channel, selectable identity tagging (MCSIT) data translator includes a word monitor port and a channel identifier (ID) tagger. The word monitor port is configured to receive a word generated by a specified one of a plurality of controllable components. The word includes no identifying information for the specified controllable component. The word monitor port is also configured to generate a channel ID corresponding to the specified controllable component and a word type corresponding to the word. The channel ID tagger is configured to determine whether to tag the word with the channel ID based on the word type and, based on the determination, to generate a processed word.

In a wireless docking system a dockee device (120) communicates with a host device (100) that is coupled to at least one peripheral (110, 111, 112). The host device has a host communication unit (102) and a docking processor (101) arranged for docking at least one dockee device. The dockee device has a dockee communication unit (121), and a dockee processor (122) for docking to the host device. The dockee processor is arranged for providing at least one virtual peripheral device in a virtual docking environment, the virtual peripheral device having a privacy level. When docking, the virtual peripherals are mapped on actual peripherals so as to apply the privacy level to the actual peripheral. When docked, data transfer with the actual peripheral is controlled according to the respective peripheral privacy level.

Described herein are systems and methods for conversion of numeric values between different number base formats, for use with software applications. In accordance with an embodiment, an integral part of a passed floating-point numeric value in a source number base (e.g., binary) format is isolated and converted to an integer. A fractional part of the numeric value is also isolated and converted to an integer, while limiting the isolation and conversion of the fractional part to a required precision or number of digits, depending on the particular requirements of a software application. The fractional part can be rounded, including determining an exact roundoff as appropriate, and if necessary propagating the rounding to the integral part. Digits from the resulting integers representing the integral and fractional parts can then be collected and used to prepare a representation of the original numeric value in a target number base (e.g., decimal) format.

Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.

Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves configured to receive transaction requests from a plurality of masters. The data structure includes one or more counters for keeping track of the number of in-flight transactions; a table that keeps track of the age of each of the in-flight transactions for each master using the one or more counters; and control logic that verifies that a transaction response for an in-flight transaction for a particular master has been issued by the slave in a predetermined order based on the tracked age for the in-flight transaction in the table.