A universal floating-point Instruction Set Architecture (ISA) compute engine implemented entirely in hardware. The ISA compute engine computes directly with human-readable decimal character sequence floating-point representation operands without first having to explicitly perform a conversion-to-binary-format process in software. A fully pipelined convertToBinaryFromDecimalCharacter hardware operator logic circuit converts one or more human-readable decimal character sequence floating-point representations to IEEE 754-2008 binary floating-point representations every clock cycle. Following computations by at least one hardware floating-point operator, a convertToDecimalCharacterFromBinary hardware conversion circuit converts the result back to a human-readable decimal character sequence floating-point representation.

A data-brokerage service that facilitates data sharing between Internet-of-Things (IoT) platforms via peer-to-peer connections is described. In various embodiments, the data-brokerage service receives, from an IoT platform acting as data consumer, a selection of data fields included in a plurality of data streams provided from a plurality of respective IoT platforms acting as data producers. Responsive to the selection, the data-brokerage service causes the plurality of data-producer platforms to stream at least the selected data fields of the plurality of data streams to the data-consumer platform, and causes the data-consumer platform to combine the streamed data fields received from the plurality of data-producer platforms into a single target data stream.

A data-brokerage service that facilitates data sharing between Internet-of-Things (IoT) platforms via peer-to-peer connections is described. In various embodiments, the data-brokerage service receives, from an IoT platform acting as data consumer, a selection of data fields included in a plurality of data streams provided from a plurality of respective IoT platforms acting as data producers. Responsive to the selection, the data-brokerage service causes the plurality of data-producer platforms to stream at least the selected data fields of the plurality of data streams to the data-consumer platform, and causes the data-consumer platform to combine the streamed data fields received from the plurality of data-producer platforms into a single target data stream.

A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware H=20 convertFromDecimalCharacter conversion operators.

A universal floating-point Instruction Set Architecture (ISA) implemented entirely in hardware. Using a single instruction, the universal floating-point ISA has the ability, in hardware, to compute directly with dual decimal character sequences up to IEEE 754-2008 “H=20” in length, without first having to explicitly perform a conversion-to-binary-format process in software before computing with these human-readable floating-point or integer representations. The ISA does not employ opcodes, but rather pushes and pulls “gobs” of data without the encumbering opcode fetch, decode, and execute bottleneck. Instead, the ISA employs stand-alone, memory-mapped operators, complete with their own pipeline that is completely decoupled from the processor's primary push-pull pipeline. The ISA employs special three-port, 1024-bit wide SRAMS; a special dual asymmetric system stack; memory-mapped stand-alone hardware operators with private result buffers having simultaneously readable side-A and side-B read ports; and dual hardware H=20 convertFromDecimalCharacter conversion operators.

Systems, methods, and machine-readable instructions stored on machine-readable media are disclosed for selecting, based on an analysis of a first process executing on a first host, at least one of a plurality of other hosts to which to migrate the first process, the selecting being further based on an analysis of the plurality of the other hosts and an analysis of processes executing on the plurality of the other hosts. At least one predictive analysis technique is used to predict an amount of time to complete migrating the first process to the selected at least one of the plurality of other hosts and an end time of the second process. In response to determining that a current time incremented by the predicted amount of time to complete migrating the first process is later than or equal to the predicted end time of the second process, a migration time at which to migrate the first process from the first host to the selected at least one of the plurality of other hosts is scheduled. At the scheduled migration time, the migration of the first process from the first host to the selected at least one of the plurality of other hosts is performed.

Systems, methods, and machine-readable instructions stored on machine-readable media are disclosed for selecting, based on an analysis of a first process executing on a first host, at least one of a plurality of other hosts to which to migrate the first process, the selecting being further based on an analysis of the plurality of the other hosts and an analysis of processes executing on the plurality of the other hosts. At least one predictive analysis technique is used to predict an amount of time to complete migrating the first process to the selected at least one of the plurality of other hosts and an end time of the second process. In response to determining that a current time incremented by the predicted amount of time to complete migrating the first process is later than or equal to the predicted end time of the second process, a migration time at which to migrate the first process from the first host to the selected at least one of the plurality of other hosts is scheduled. At the scheduled migration time, the migration of the first process from the first host to the selected at least one of the plurality of other hosts is performed.

In implementations of systems for font replacement in print workflows, a computing device implements a print system to receive print request data describing a document having a corpus of text rendered using a font that is not available to the print system. The print system extracts the corpus of text from the document and generates an indication of a context category of the corpus of text using a machine learning model training to classify context categories of text inputs using training data describing a different corpus of text. A replacement font is identified based on the indication of the context category from replacement font data describing a plurality of candidate replacement fonts. The printing system generates a raster image depicting the corpus of text rendered using the replacement font.

Methods and apparatuses for compressing drive curves for scanning devices and corresponding computer programs are provided. In this case, a drive curve is decomposed into segments. Segments which are not yet present in a library are stored in the library. Moreover, for each segment a pointer to a corresponding segment in the library is stored in a list.

A novel and useful system and method of input alignment for streamlining vector operations that reduce the required memory read bandwidth. The input aligner as deployed in the NN processor, functions to facilitate the reuse of data read from memory and to avoid having to re-read that data in the context of neural network calculations. The input aligner functions to distribute input data (or weights) to the appropriate compute elements while consuming input data in a single cycle. Thus, the input aligner is operative to lower the required read bandwidth of layer input in an ANN. This reflects the fact that normally in practice, a vector multiplication is performed every time instance. This considers the fact that in many native calculations that take place in an ANN, the same data point is involved in multiple calculations.