Methods and apparatuses providing file type inspection in firewalls by moving the flow between deep inspection file and lightweight accelerated paths. The method includes obtaining, by a network security device, a packet flow of a file transfer session in which at least two files are transferred and determining, by the network security device, at least an offset parameter based on at least one attribute of at least a first packet in the packet flow. The offset parameter is for a first file being transferred of the at least two files and relates to an expected positon of a control data sequence within the packet flow. In this method, based on the offset parameter, directing, by the network security device, to an accelerated packet inspection path instead of to a deep packet inspection path, a portion of the packet flow including one or more packets that follow the first packet.

A portable electronic device includes a display, an operation receiver, and a controller. The display displays a menu screen including menu items. The operation receiver receives a user operation on the menu screen. The controller controls the display according to the user operation via the operation receiver. The menu screen further includes: first tab information indicating a category for classifying the menu items; second tab information indicating a plurality of sub categories included in the category; and third tab information indicating, for each of the sub categories, a menu item set number in which menu items in one sub category are partitioned to be displayed per a set on the menu screens. The controller changes menu items to be displayed on the menu screen, according to a user operation input via the operation receiver with the first, second, and third tab information displayed on the menu screen.

The present disclosure provides a write cache circuit, a data write method, and a memory. The write cache circuit includes: a control circuit configured to generate, on the basis of a mask write instruction, a first write pointer and a pointer to be positioned, generate a second write pointer on the basis of a write command, generate a first output pointer on the basis of a mask write shift instruction, and generate a second output pointer on the basis of a write shift instruction; a first cache circuit configured to cache, on the basis of the first write pointer, the pointer to be positioned and output a positioned pointer on the basis of the first output pointer, the positioned pointer being configured to instruct a second cache circuit to output a write address written by the second write pointer generated according to the mask write instruction.

An embodiment of the present invention is directed to an innovative approach to installing, upgrading and downgrading the package irrespective of the kernel version during system boot time after an operating system (OS) patching kernel update.

In a system for the administration of a group of imaging devices which are equipped with a corresponding device hosts, device software and a configuration protocol are executably stored on the device host. The system can include a distributed database system which configured to receive configuration protocols from the device host and to store modified configuration protocols for the respective device host, and to distribute modified configuration protocols. The received and/or stored configuration protocols are made available via a central write access. The system can include an administrator having a memory, a user interface and a processor for communicating with the distributed database system. Configuration protocols can be modified via the user interface and sent to the distributed database system for storage and/or distribution to at least one selected imaging device. These aspects are also applicable to a method for the administration of imaging devices.

A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

Provided are an information processing program, an information processing device, and an information processing method that enable application processing and data transmission in a non-blocking manner to increase a communication speed. A server device includes buffering means configured to accumulate events, socket writing means configured to process the events, and flag management means configured to exclusively set a flag. The socket writing means includes socket write request means and callback processing means. The flag management means exclusively sets the flag at a timing before the event processing requested by the socket write request means starts, and releases the flag at a timing after the processing by the callback processing means ends. The socket write request means receives a call, and in a case where the flag is set, the events accumulated by the buffering means are processed.

Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed.

In response to starting a system including a first non-volatile memory containing system boot code, and a second non-volatile memory, provisioning of the second non-volatile memory is performed. The provisioning includes checking that the second non-volatile memory is uninitialized, and in response to determining that the second non-volatile memory is uninitialized, the system boot code is copied from the first non-volatile memory to the second non-volatile memory.

An egress packet modifier includes a script parser and a pipeline of processing stages. Rather than performing egress modifications using a processor that fetches and decodes and executes instructions in a classic processor fashion, and rather than storing a packet in memory and reading it out and modifying it and writing it back, the packet modifier pipeline processes the packet by passing parts of the packet through the pipeline. A processor identifies particular egress modifications to be performed by placing a script code at the beginning of the packet. The script parser then uses the code to identify a specific script of opcodes, where each opcode defines a modification. As a part passes through a stage, the stage can carry out the modification of such an opcode. As realized using current semiconductor fabrication process, the packet modifier can modify 200M packets/second at a sustained rate of up to 100 gigabits/second.