A memory device comprises a memory control unit including a processor configured to control operation of the memory array according to a first memory management protocol for memory access operations, the first memory management protocol including boundary conditions for multiple operating conditions comprising program/erase (P/E) cycles, error management operations, drive writes per day (DWPD), and power consumption; monitor operating conditions of the memory array for the P/E cycles, error management operations, DWPD, and power consumption; determine when a boundary condition for one of the multiple operating conditions is met; and in response to determining that a first boundary condition for a first monitored operating condition is met, change one or more operating conditions of the first memory management protocol to establish a second memory management protocol for the memory access operations, the second memory management protocol including a change boundary condition of a second monitored operating condition.

Techniques are described herein for predicting disk drive failure using a machine learning model. The framework involves receiving disk drive sensor attributes as training data, preprocessing the training data to select a set of enhanced feature sequences, and using the enhanced feature sequences to train a machine learning model to predict disk drive failures from disk drive sensor monitoring data. Prior to the training phase, the RNN LSTM model is tuned using a set of predefined hyper-parameters. The preprocessing, which is performed during the training and evaluation phase as well as later during the prediction phase, involves using predefined values for a set of parameters to generate the set of enhanced sequences from raw sensor reading. The enhanced feature sequences are generated to maintain a desired healthy/failed disk ratio, and only use samples leading up to a last-valid-time sample in order to honor a pre-specified heads-up-period alert requirement.

In exemplary aspects of optimizing data centers, historical data corresponding to a data center is collected. The data center includes a plurality of systems. A data center representation is generated. The data center representation can be one or more of a schematic and a collection of data from among the historical data. The data center representation is encoded into a neural network model. The neural network model is trained using at least a portion of the historical data. The trained model is deployed using a first set of inputs, causing the model to generate one or more output values for managing or optimizing the data center with respect to design and risk aspects.

Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

This application relates to a computing system and method for an automated program error repair. In one aspect, the computing system includes a storage, a preprocessing processor, and an automated error repair processor. The storage stores a program code. The preprocessing processor acquires the program code from the storage and preprocesses the program code. Preprocessing includes tokenizing the program code with tokens, converting the tokens into vectors, and adding location information for the tokens. The automated error repair processor receives the preprocessed program code as an input from the preprocessing processor, detects an error in the preprocessed program code, corrects the detected error, and outputs the error-corrected program code. Detecting and correcting the error are performed based on a deep learning result and the location information for the tokens.

A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.

This disclosure describes systems, methods, and devices related to an enhanced retry count for an uplink (UL) multi-user (MU) transmission. A device may identify a trigger frame received from a first device on a wireless communication channel. The device may determine a quality of service counter associated with an access category. The device may cause to send a frame to the first device based at least in part on the trigger frame. The device may determine an error condition associated with the frame. The device may refrain from incrementing the quality of service counter based on the error condition.

Techniques manage a redundant array of independent disks. In such a technique, a response time of a first storage device in the RAID is compared to a first threshold. In response to the response time of the first storage device exceeding the first threshold, the first storage device is configured as a pseudo-degraded storage device, such that the pseudo-degraded storage device is responsive to write requests only.

Techniques for database and file management herein include a processor and a memory device storing instructions that cause the processor to perform operations comprising creating a request based on an extensible markup language (XML) or an interpreted scripting language object, wherein the request comprises unauthenticated data for validation. The operations can also include transmitting the request to a remote device), updating metadata corresponding to the request to indicate the successful validation by the remote device, validating a response file, and detecting a discrepancy between the unauthenticated data and the authenticated data accessible by the remote device. Additionally, the operations include obtaining correction data to resolve the discrepancy, and executing a transaction based on the request and the correction data.

A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.