An aspect of behavior of an embedded system may be determined by (a) determining a baseline behavior of the embedded system from a sequence of patterns in real-time digital measurements extracted from the embedded system; (b) extracting, while the embedded system is operating, real-time digital measurements from the embedded system; (c) extracting features from the real-time digital measurements extracted from the embedded system while the embedded system was operating; and (d) determining the aspect of the behavior of the embedded system by analyzing the extracted features with respect to features of the baseline behavior determined.

An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

A method and an apparatus for verifying an operation state of an application are provided. The method can include setting target verification operation information according to an operation verification item of an application to be verified; setting a verification process instruction for the target verification operation information; encapsulating the verification operation information and the verification process instruction as fault injection data, and sending the fault injection data to a data input port of the application to be verified; matching the process feedback information with the verification process instruction in response to receiving the process feedback information corresponding to the fault injection data, and determining executed target verification operation information.

Techniques for identifying and remedying performance issues of Virtualized Network Functions (VNFs) are discussed. An example method includes outputting a request to a network Element Manager (EM) to create a Virtualized Network Function (VNF) Performance Measurement (PM) job to collect VNF PM data from a VNF and receiving a set of VNF PM data associated with the VNF from the EM. The set of VNF PM data is processed associated with the VNF. A request to the EM is output to create a Virtualization Resource (VR) PM job to collect, through a VNF Manager (VNFM) and a virtualized infrastructure manager (VIM), VR PM data from a VR used by the VNF. Then a set of VR PM data is received from the EM and processed.

Data to be stored at a memory sub-system can be received from a host system. A portion of the host data that includes user data and another portion of the host data that includes system metadata can be determined. A mapping for a data structure can be received that identifies locations of the data structure that are fixed with respect to an encoding operation and locations of the data structure that are not fixed with respect to the encoding operation. The data structure can be generated for the user data and system metadata based on the mapping, and an encoding operation can be performed on the data structure to generate a codeword.

An example system includes a server communicatively connected to a cellular base transceiver station having an RF coverage area and configured for RF communication with a first entity that is a transceiver device in the RF coverage area, wherein the server comprises a first publish-subscribe broker that is part of a publish-subscribe broker network that comprises one or more publish-subscribe brokers, wherein a second entity connected to any of the one or more publish-subscribe brokers in the publish-subscribe broker network accepts communications from the transceiver device if the second entity subscribes to data packets published by the transceiver device, and wherein the data packets published by the transceiver device are routed through the publish-subscribe broker to which the second entity is connected.

An example system includes a server communicatively connected to a cellular base transceiver station having an RF coverage area and configured for RF communication with a first entity that is a transceiver device in the RF coverage area, wherein the server comprises a first publish-subscribe broker that is part of a publish-subscribe broker network that comprises one or more publish-subscribe brokers, wherein a second entity connected to any of the one or more publish-subscribe brokers in the publish-subscribe broker network accepts communications from the transceiver device if the second entity subscribes to data packets published by the transceiver device, and wherein the data packets published by the transceiver device are routed through the publish-subscribe broker to which the second entity is connected.

A method, a system, and a computer program product for analyzing error messages. A first error log generated as a result of an execution of at least one task of a computing system at a first instance is received. The first error log include a plurality of first error messages. A first association rules model is generated using the first error messages. The first association rules model includes a plurality of association rules defining one or more relationships. A second error log, including a plurality of second error messages, generated as a result of an execution of the task at a second instance is received and a second association rules model is generated using the second error messages. Based on the first and second association rules models, at least one error message pattern associated with execution of the at least one task is determined.

A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.