G06F12/00

Cache block budgeting techniques
11556479 · 2023-01-17 · ·

Methods, systems, and devices for cache block budgeting techniques are described. In some memory systems, a controller may configure a memory device with a cache. The cache may include a first subset of blocks configured to statically operate in a first mode and a second subset of blocks configured to dynamically switch between operating in the first mode and a second mode. A block operating in the second mode may be configured to store relatively more bits per memory cell than a block operating in the first mode. The controller may track and store, for each block of the second subset of blocks, a respective ratio of cycles performed in the first mode to cycles performed in the second mode. The controller may select a block from the second subset of blocks to switch between modes responsive to a trigger and based on the respective ratio for the block.

Managing storage systems that are synchronously replicating a dataset

Managing storage systems that are synchronously replicating a dataset, including: detecting a change in membership to the set of storage systems synchronously replicating the dataset; and applying one or more membership protocols to determine a new set of storage systems to synchronously replicate the dataset, wherein the one or more membership protocols include a quorum protocol, an external management protocol, or a racing protocol, and wherein one or more I/O operations directed to the dataset are applied to a new set of storage systems.

Direct map memory extension for storage class memory

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to receive a first request to allocate a direct swap file associated with an application stored in a system memory on a persistent storage media, and map a linear and continuous space of the persistent storage media to the direct swap file associated with the application in response to the first request. Other embodiments are disclosed and claimed.

System and method of selectively restoring a computer system to an operational state

Disclosed herein are systems and method for selectively restoring a computer system to an operational state. In an exemplary aspect, the method may create a backup image of the computer system comprising a set of data blocks, and create and start a virtual machine based on the backup image. The method may identify a subset of the data blocks accessed from the backup image during startup of the virtual machine. In response to determining that the computer system should be restored, the method may restore the subset of the data blocks such that the computer system is operational during startup, and restore a remaining set of the data blocks from the backup image after the startup of the computer system.

Memory access collision management on a shared wordline

A processing device in a memory sub-system sends a program command to the memory device to cause the memory device to initiate a program operation on a corresponding wordline and sub-block of a memory array of the memory device. The processing device further receives a request to perform a read operation on data stored on the wordline and sub-block of the memory array, sends a suspend command to the memory device to cause the memory device to suspend the program operation, reads data corresponding to the read operation from a page cache of the memory device, and sends a resume command to the memory device to cause the memory device to resume the program operation.

Storage system for enhancing data valid windows of signals

A storage system includes: a memory controller which provides a clock signal; a buffer which receives the clock signal and re-drives the clock signal, the buffer including a sampler which receives a data signal and a data strobe signal regarding the data signal, and which outputs a data stream; and a nonvolatile memory, including: a first duty cycle corrector, which receives the clock signal outputs a corrected clock signal by performing a first duty correction operation on the clock signal; and a data strobe signal generator, which generates the data strobe signal based on the corrected clock signal and provides the data strobe signal to the buffer. The buffer receives the data strobe signal output from the nonvolatile memory, senses a duty ratio of the data strobe signal input to the sampler, and performs a second duty correction operation on the duty ratio of the input data strobe signal.

Performance throttling based on power-off time
11698731 · 2023-07-11 · ·

Responsive to a power-on of a memory device, an elapsed power-off time is identified based on a difference between a time at which the power-on occurred and a time at which a previous power-off of the memory device occurred. Responsive to a determination that the elapsed power-off time satisfies the elapsed time threshold criterion, a request to perform a first write operation on a memory unit of the memory device since power on is received, a performance parameter associated with the memory unit of the memory device is changed to a first parameter value that corresponds to a reduced performance level, and the write operation is performed on the memory unit of the memory device in accordance with the first parameter value that corresponds to the reduced performance level. Responsive to completion of the write operation, the performance parameter is changed to a value that corresponds to a normal performance level.

Data storage volume re-bind method
11698838 · 2023-07-11 · ·

Disclosed herein is a technique to automatically re-bind applications and storage volumes during recovery from planned outage or platform failure and disaster recovery. Such implementations can involve managing volume management information that maps volume claim information with a logical volume identifier associated with persistent volume information; and for receipt of a request for a new volume, referencing the volume management information to retrieve an associated logical volume identifier and the persistent volume information based on the volume claim information associated with the request; and providing the retrieved persistent volume information to a volume provisioning function.

Multiple data channel memory module architecture

According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Protocol for refresh between a memory controller and a memory device
11551741 · 2023-01-10 · ·

The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.