A method of preserving the contiguity of large pages of a workload during migration of the workload from a source host to a destination host includes the steps of: detecting at the destination host, receipt of a small page of zeros from the source host, wherein, at the source host, the small page is part of one of the large pages of the workload; and upon detecting the receipt of the small page of zeros, storing, at the destination host, all zeros in a small page that is part of one of the large pages of the workload.

The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.

A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

A method for reprogramming data of a software function executed by an execution core and a security core, the data being present in two physically separate non-volatile memories, each managed by one of the execution or security cores, including the following steps: upon receiving a reprogramming request, a second value is stored in a first Boolean, determining whether the first Boolean is equal to the second value and if a second Boolean is equal to a first value, and if affirmative; an execution core is made to emit at a reinitialization request via a bidirectional communication channel towards a security core and a request to initialize a portion of the first non-volatile memory towards the set of functions for managing the non-volatile memory by an execution core; a second value is stored in the second Boolean; it is determined whether a predetermined reprogramming event has taken place, and if affirmative, the first value is stored in the first Boolean, while keeping the second value in the second Boolean, and each security core is made to emit a request to write predetermined stored values to the set of functions for managing the memory associated with the non-volatile memory managed by the security core.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

The present disclosure relates to an emulation test system for flash translation layer and a method thereof, the system comprising a network block device, a virtual hardware accelerator, a flash translation layer module, and a virtual flash memory based on the network block device, wherein the network block device is configured to receive and forward test information, the test information including a read instruction and/or a write instruction and data to be written; the virtual hardware accelerator is configured to allocate the test information to each thread of the virtual hardware accelerator and perform virtual hardware acceleration on the flash translation layer module; and the flash translation layer module is configured to operate the virtual flash memory based on the test information to obtain an operation result.

A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.

A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.