Patent classifications
G06F12/00
Backup, restoration, and migration of computer systems
Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for backup, restoration, and migration of computer systems. In some implementations, data from a first server environment is obtained. A data package is generated that includes configuration data, data objects, and/or metadata from the first server environment organized in a predetermined arrangement. Data indicating (i) a destination on which to deploy the archived data from the first server environment and (ii) one or more characteristics of the destination is received. Mapping data that specifies a mapping of elements in the predetermined arrangement to elements of server environments having the one or more characteristics is accessed. Server environment data derived from the data package is deployed, the server environment data being deployed to the destination and arranged at the destination in a manner specified by the mapping data.
Method, apparatus and computer program product for managing backup system
Embodiments of the present disclosure provide a method, device, and computer program product for managing a backup system. The method comprises obtaining a state of a backup system, wherein the backup system comprises a plurality of backup servers and a plurality of backup clients, the plurality of backup servers is communicatively coupled to the plurality of backup clients via a network, and wherein at least one backup server from the plurality of backup servers is configured to back up data of at least one backup client allocated from the plurality of backup clients to the at least one backup server, determining a reward score corresponding to the state of the backup system and, determining, based on the state of the backup system and the reward score, configuration information for the backup system, the configuration information indicating allocation of the plurality of backup clients to the plurality of backup servers.
Method and system for asset protection threat detection and mitigation using interactive graphics
A method and system for asset protection threat detection and mitigation using interactive graphics. Specifically, the disclosed method and system entail discerning protection vulnerabilities exhibited by assets (or databases) based on maintained backup metadata. These protection vulnerabilities may subsequently be visualized as part of a projected graphical user interface, which may not only disclose the protection vulnerabilities to a user but also may enable the user to rectify the disclosed protection vulnerabilities through on-demand asset backup operations.
Data compression and encryption based on translation lookaside buffer evictions
A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.
Data storage migration in replicated environment
The described technology is generally directed towards replicating metadata representing a virtual data structure corresponding to replicated legacy data instead of the actual data for the data structure. Once virtual chunks are replicated to a remote, newer storage system, the corresponding legacy data is locally read into the virtual chunks to transform the virtual chunks into real data chunks of the remote newer storage system. A checksum can be replicated for the remote newer storage system to evaluate the consistency of the data. Efficient data storage migration is thus accomplished in a replicated environment based on relatively negligible replication traffic between two remote locations, while still assuring the consistency of migrated data.
Secure memory translations
An apparatus is provided, connectable to a memory and one or more peripherals. The apparatus includes translation request circuitry to receive a translation request from one of the peripherals to translate an input address within an input domain to an output address within an output domain. Signing circuitry generates a signature of at least part of the output address using a private key. Translation response circuitry responds to the translation request by transmitting to the one of the peripherals a translation response, including the output address and the signature. Gateway circuitry receives access requests to the memory. Each of the access requests comprises a desired memory address in the output domain and a signature of the desired memory address. The gateway performs validation of the signature of the desired memory address using the private key and in response to the validation of a given access request failing, performs an error action.
Adding single disks to an array by relocating raid members
Protection group members from a cluster of W baseline size disks with RAID (D+P) protection groups associated with W partition indices, where W=D+P, are selected and relocated to a new baseline size disk using a W-by-W relocation sequence matrix. The same relocation sequence matrix is used to select and relocate protection group members from M clusters of baseline size disks to a new disk that has M times the storage capacity of each baseline size disk. A new cluster of multiple size disks is formed when W multiple size disks have been added, after which the W-by-W relocation sequence matrix is used to select and relocate protection group members from the new cluster to additional multiple size disks.
Diagonal page mapping in memory systems
A plurality of host data items, including a first host data item and a second host data item, are received. The second host data item consecutively follows the first host data item. The first host data item is stored in a first page of a first logical unit of the memory device, wherein the first page is associated with a first page number. A second page number is determined for the second host data item based on an offset value that corresponds to a number of pages per wordline of the memory device. A second logical unit of the memory device is identified. The second host data item is stored in a second page of the second logical unit, wherein the second page is identified by the second page number, and the first page and the second page are associated with a fault-tolerant stripe.
SEMICONDUCTOR DEVICE
A semiconductor device with a novel structure is provided. A plurality of memory circuits, a switching circuit, and an arithmetic circuit are included. Each of the plurality of memory circuits has a function of retaining weight data and a function of outputting the weight data to a first wiring. The switching circuit has a function of switching a conduction state between any one of the plurality of first wirings and a second wiring. The arithmetic circuit has a function of performing arithmetic processing using input data and the weight data supplied to the second wiring. The memory circuits are provided in a first layer. The switching circuit and the arithmetic circuit are provided in a second layer. The first layer is provided in a layer different from the second layer.
Memory access request for a memory protocol
A computer-implemented method includes identifying two or more memory locations and referencing, by a memory access request, the two or more memory locations. The memory access request is a single action pursuant to a memory protocol. The computer-implemented method further includes sending the memory access request from one or more processors to a node and fetching, by the node, data content from each of the two or more memory locations. The computer-implemented method further includes packaging, by the node, the data content from each of the two or more memory locations into a memory package, and returning the memory package from the node to the one or more processors. A corresponding computer program product and computer system are also disclosed.