A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

A throughput division means (11) divides a throughput of a communication between a video delivery server configured to deliver, in a plurality of delivery modes, video data to a user terminal device used by a user and the user terminal device in a delivery period of the video data, according to a period of each delivery mode. A playback bit rate estimation means (12) estimates a playback bit rate of the video data, based on a throughput divided according to a period of the delivery mode. Thus, estimation precision of a video playback bit rate can be improved even when a video delivery server delivers video data in a plurality of delivery modes.

Disclosed are devices and methods for protecting the register file of a power management integrated circuit (PMIC). In one embodiment, a device is disclosed comprising: a register file comprising a plurality of a registers, at least one register in the register file containing a write register bit (WRB); and an interface configured to receive messages from a host application, the messages including a WRB enablement signal, wherein the device is configured to enable writing to the register file in response to receiving the WRB enablement signal over the interface, write data in response to write messages while writing to the register file is enabled, and disable writing to the register file in response to receiving a stop bit over the interface.

A service linkage assistance device 5 includes an executing unit 51 which accepts a request for a stateless API for a stateful service which exposes a stateful API from a service linkage device 1 which executes a linkage service obtained by linking multiple services including the stateful service, interprets the request, and executes the stateful API and a storage unit 52 which stores dynamic information included in a response from the stateful API, and the stateless API is exposed to the service linkage device 1 by the service linkage assistance device 5.

The present disclosure relates to an information processing device and a method capable of implementing more various communications.

In a space of a user, an input of information by the user is accepted, and tag information for associating control information for controlling occurrence of an event for a communication partner of the user with a space of the communication partner is generated using the accepted information. Furthermore, it is determined whether or not an occurrence condition of the event designated by the tag information for associating the control information for controlling the occurrence of the event for the communication partner with the space of the communication partner, the tag information associated with the space of the user is satisfied, and in a case where it is determined that the occurrence condition is satisfied, the event designated by the tag information is allowed to occur. The present disclosure may be applied to, for example, an information processing device, an image processing device, an electronic device, an information processing method, a program or the like.

A plug-in mobile peripheral component interconnect express module connector is disclosed, comprising a plastic body, and a first terminal set and a second terminal set disposed relatively in the plastic body. The plastic body includes transversely penetrated slots, an upper end surface of the slots has intermittently plural upper magazines, and a lower end surface has intermittently plural lower magazines. The first terminal set includes plural first elastic terminals inserted in the upper magazines, and the second terminal set includes plural second elastic terminals inserted in the lower magazines. Each first elastic terminal is opposed to each second elastic terminal, forming a holding gap. A motherboard is inserted between the first elastic terminals and the second elastic terminals from a side, and an MXM board is inserted between the first elastic terminals and the second elastic terminals from the other side.

Methods, apparatus, and computer platforms and architectures employing many-to-many and many-to-one peripheral switches. The methods and apparatus may be implemented on computer platforms having multiple nodes, such as those employing a Non-uniform Memory Access (NUMA) architecture, wherein each node comprises a plurality of components including a processor having at least one level of memory cache and being operatively coupled to system memory and operatively coupled to a many-to-many peripheral switch that includes a plurality of downstream ports to which NICs and/or peripheral expansion slots are operatively coupled, or a many-to-one switch that enables a peripheral device to be shared by multiple nodes. During operation, packets are received at the NICs and DMA memory writes are initiated using memory write transactions identifying a destination memory address. The many-to-many and many-to-one peripheral switches forwards the transaction packets internally within the switch based on the destination address such that the packets are forwarded to a node via which the memory address can be accessed. The platform architectures may also be configured to support migration operations in response to failure or replacement of a node.

An exemplary method of controlling a server that can provide a game can include associating a user with a group; determining, based on information related to activity of the user in at least one of the game and an event within the game, information related to activity of the group with which the user is associated; and providing a bonus to the group based on the information related to activity of the group.

The present disclosure relates scaling out servers that performs Layer 3 (L3) termination. In particular, the server includes: a packet receiving unit which receives a packet from any load balancer performing L3 termination via an Layer 2 (L2) switch; an assignment unit which, by referencing a MAC/MARK number correspondence table in a storage unit, assigns to the received packet a MARK number that corresponds to a transmission source MAC address; a recording unit which records a MARK number for connection of the received packet in a connection/MARK number correspondence table; and a packet transmission unit which, when a reply packet to the received packet is to be transmitted, routes the reply packet via the L2 switch by acquiring, from a MARK number/GW correspondence table in the storage unit, an IP address of a load balancer corresponding to the MARK number associated with the connection of the received packet.