Techniques are described for offloading remote direct memory operations (RDMOs) to “execution candidates”. The execution candidates may be any hardware capable of performing the offloaded operation. Thus, the execution candidates may be network interface controllers, specialized co-processors, FPGAs, etc. The execution candidates may be on a machine that is remote from the processor that is offloading the operation, or may be on the same machine as the processor that is offloading the operation. Details for certain specific RDMOs, which are particularly useful in online transaction processing (OLTP) and hybrid transactional/analytical (HTAP) workloads, are provided.

An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.

An information processing apparatus is provided for communicating with another information processing apparatus in a different site by using at least one of a plurality of communication platforms. The information processing apparatus includes: a receiving unit configured to receive a transmission image that has been transmitted from the another information processing apparatus in the different site; a displaying unit configured to display on a display device the transmission image that has been received by the receiving unit; and a reading unit configured to read an image to be displayed from an image storing unit configured to store the image to be displayed. For at least a certain period while the one of the communication platform is being switched to another one, the displaying unit displays, in place of the transmission image, the image to be displayed that has been read by the reading unit.

A system for communicating over a Controller Area Network (CAN) bus may include a central controller and a plurality of smart devices communicatively coupled with the central controller over the CAN bus and over an identification verification network separate from the CAN bus. Each smart device may be configured to at least one of measure various parameters and control a function based on a command received from the central controller, and then communicate one or more signals indicative of at least one of the measured parameters and the function over the CAN bus to the central controller. Each of the smart devices may include a physical input, a physical output, and at least two nonvolatile memory locations. A first of the at least two memory locations may be configured to store an identifier input signal received at the physical input from at least one of the central controller and an upstream smart device over the identification verification network, the identifier input signal being stored by the smart device as a function instance value for the smart device. The smart device may further include a source address determination module configured to determine a source address for the smart device based on the function instance value and a factory default base address for the smart device, and store the source address in a second of the at least two memory locations.

In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

Apparatuses for controlling data transaction between master and slave devices are described. A master port connected to a master device can include a voltage regulator, a bridging circuit connected to a network element, and a redriver circuit. In response to a data transaction corresponding to a first type of data transaction, the master port can activate the voltage regulator and deactivate the redriver circuit to support a first operation mode causing the master device to perform the data transaction with a slave device via the network element. In response to the data transaction corresponding to a second type of data transaction, the master port can deactivate the voltage regulator and activate the redriver circuit to support a second operation mode causing the master port to disconnect from a slave port connected to the slave device and the data transaction is fulfilled by a circuit connected to the slave device.

In order to solve a conventional problem that it is not possible to manage partial content in a webpage as a block and execute processing on the block, a webpage processing apparatus 7 includes: a block information storage unit 711 in which one or more pieces of block information each having a block identifier for identifying a block, which is partial content in a webpage, and location identifying information for specifying a location of the block in the webpage are stored; a block processing unit 731 that executes block processing, which is processing regarding a block specified with block information, using location identifying information contained in any one of the one or more pieces of block information; and a result output unit 751 that outputs a block processing result, which is a result of the block processing. Accordingly, it is possible to manage a block, which is partial content in a webpage, and execute processing on the block.

An imaging device includes: a communication unit that communicates by use of both or one of a first communication scheme and a second communication scheme capable of communicating at a higher speed than the first communication scheme; a determination unit that determines whether the second communication scheme is available; and a function control unit that performs control related to a function according to a determination result of the determination unit.

The present disclosure has a configuration in which a distributor who performs a separate distribution that is different from this live content, or a viewer who views this separate distribution can participate in a virtual space and express intent or participate in visual recognition through the commitment of a virtual item.