A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

In a hybrid computing system including at least one analog processor and at least one digital processor an embedded problem is repeatedly run or executed on the analog processor(s) to generate a first plurality of candidate solutions to the computational problem, the candidate solutions are returned to the digital processor(s) which determine a value for at least one statistical feature of the candidate solutions, at least one programmable parameter of the plurality of analog devices in the analog processor(s) is adjusted to at least partially compensate for deviations from an expected value of the at least one statistical feature, the expected value of the at least one statistical feature inferred from the structure of the embedded problem, the embedded problem is again repeatedly run or executed on the analog processor(s) to generate a second plurality of candidate solutions to the computational problem.

In a hybrid computing system including at least one analog processor and at least one digital processor an embedded problem is repeatedly run or executed on the analog processor(s) to generate a first plurality of candidate solutions to the computational problem, the candidate solutions are returned to the digital processor(s) which determine a value for at least one statistical feature of the candidate solutions, at least one programmable parameter of the plurality of analog devices in the analog processor(s) is adjusted to at least partially compensate for deviations from an expected value of the at least one statistical feature, the expected value of the at least one statistical feature inferred from the structure of the embedded problem, the embedded problem is again repeatedly run or executed on the analog processor(s) to generate a second plurality of candidate solutions to the computational problem.

A hybrid wave computer that computes an inputted original signal as frequency information includes: an input module configured to separate a frequency of the original signal by detecting an oscillation of an piezoelectric element by each position as the original signal having an embedded frequency of several bands is transmitted in a form of acoustic waves on a substrate provided with the piezoelectric element; a calculation module including at least one vibration amplifier or vibration damper for receiving the frequency of the original signal separated in the input module and amplifying or attenuating a wave for each frequency band to calculate the inputted original signal in a frequency band; and a storage module configured to store binarized frequency information in the calculation module as digital information, so that the original signal is interfaced in a form of waves.

In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

A hybrid analog and digital computational system is created by receiving equations in which a set of solution values is unknown. A residual iterative algorithm is implemented to solve the set of solution values for the equations. The residual iterative algorithm includes an outer update loop computed using a digital computing device with a set of residue values initially set to a first initial value and a set of solution update values set to a second initial value. The residual iterative algorithm includes an inner residual loop, which is iteratively computed using an analog accelerator until one or more inner residual loop stopping criteria is met and returning the set of solution update values. Next, the set of solution updates are used to update the set of residue values and a range of a next set of solution update values, thereby adjusting a computational precision of the inner residual loop.

A hybrid analog and digital computational system is created by receiving equations in which a set of solution values is unknown. A residual iterative algorithm is implemented to solve the set of solution values for the equations. The residual iterative algorithm includes an outer update loop computed using a digital computing device with a set of residue values initially set to a first initial value and a set of solution update values set to a second initial value. The residual iterative algorithm includes an inner residual loop, which is iteratively computed using an analog accelerator until one or more inner residual loop stopping criteria is met and returning the set of solution update values. Next, the set of solution updates are used to update the set of residue values and a range of a next set of solution update values, thereby adjusting a computational precision of the inner residual loop.