A probability distribution corresponding to the kernel function is determined and weights are sampled from the determined probability distribution corresponding to the given kernel function. Memristive devices of an analog crossbar are programmed based on the sampled weights, where each memristive device of the analog crossbar is configured to represent a corresponding weight. Two matrix-vector multiplication operations are performed on an analog input x and an analog input y using the programmed crossbar and a dot product is computed on results of the matrix-vector multiplication operations.

A probability distribution corresponding to the kernel function is determined and weights are sampled from the determined probability distribution corresponding to the given kernel function. Memristive devices of an analog crossbar are programmed based on the sampled weights, where each memristive device of the analog crossbar is configured to represent a corresponding weight. Two matrix-vector multiplication operations are performed on an analog input x and an analog input y using the programmed crossbar and a dot product is computed on results of the matrix-vector multiplication operations.

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R.sub.on or R.sub.off to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R.sub.on or R.sub.off to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

A processing element includes an analog operation circuit configured to receive input data from an input buffer and to generate one or more output currents associated with a multiplication operation of the input data and weights based on a bit-precision of stored weights, one or more analog-to-digital converters (ADCs) each configured to convert the one or more output currents into one or more digital codes, and a digital operation circuit configured to perform an addition operation using the one or more digital codes based on the bit-precision of the weight and to perform a summation operation on a resultant value of the addition operation based on a bit-precision of the input data.

A processing element includes an analog operation circuit configured to receive input data from an input buffer and to generate one or more output currents associated with a multiplication operation of the input data and weights based on a bit-precision of stored weights, one or more analog-to-digital converters (ADCs) each configured to convert the one or more output currents into one or more digital codes, and a digital operation circuit configured to perform an addition operation using the one or more digital codes based on the bit-precision of the weight and to perform a summation operation on a resultant value of the addition operation based on a bit-precision of the input data.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

A hybrid structure for computing-in-memory applications includes a memory cell and a digital-analog-hybrid local computing cell. The memory cell stores a weight. The digital-analog-hybrid local computing cell has a plurality of input lines, a digital output line and an analog output line. The input lines are configured to transmit a plurality of multi-bit input values. The digital-analog-hybrid local computing cell includes a digital local computing cell and a voltage local computing cell. The digital local computing cell receives the weight and is configured to generate a digital output value on the digital output line according to a higher bit of the multi-bit input values multiplied by the weight. The voltage local computing cell receives the weight and is configured to generate an analog output value on the analog output line according to a lower bit of the multi-bit input values multiplied by the weight.

A hybrid structure for computing-in-memory applications includes a memory cell and a digital-analog-hybrid local computing cell. The memory cell stores a weight. The digital-analog-hybrid local computing cell has a plurality of input lines, a digital output line and an analog output line. The input lines are configured to transmit a plurality of multi-bit input values. The digital-analog-hybrid local computing cell includes a digital local computing cell and a voltage local computing cell. The digital local computing cell receives the weight and is configured to generate a digital output value on the digital output line according to a higher bit of the multi-bit input values multiplied by the weight. The voltage local computing cell receives the weight and is configured to generate an analog output value on the analog output line according to a lower bit of the multi-bit input values multiplied by the weight.