A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

An architecture for a multiplier-accumulator (MAC) uses a common Unit Element (UE) for each aspect of operation, the MAC formed as a plurality of MAC UEs, a plurality of Bias UEs, and a plurality of Analog to Digital Conversion (ADC) UEs which collectively perform a scalable MAC operation and generate a binary result. Each MAC UE, BIAS UE and ADC UE comprises groups of NAND gates with complementary outputs arranged in NAND-groups, each NAND gate coupled to a differential charge transfer bus through a binary weighted charge transfer capacitor to form an analog multiplication product as a charge applied to the differential charge transfer bus. The analog charge transfer bus is coupled to groups of ADC UEs with an ADC controller which enables and disables the ADC UEs using successive approximation to determine the accumulated multiplication result.

Described herein are techniques of using a hybrid analog-digital processor to perform matrix operations. The hybrid analog-digital may store digital values in memory encoded in a low bit number format. The hybrid analog-digital processor may perform, using an analog processor, a matrix operation to obtain output(s). The output(s) may be encoded in the number format. The hybrid analog-digital processor may determine, using the output(s), an unbiased estimate of a matrix operation result. The hybrid analog-digital processor may store, in the memory, the unbiased estimate of the matrix operation result encoded in the number format.

Described herein are techniques of using a hybrid analog-digital processor to perform matrix operations. The hybrid analog-digital may store digital values in memory encoded in a low bit number format. The hybrid analog-digital processor may perform, using an analog processor, a matrix operation to obtain output(s). The output(s) may be encoded in the number format. The hybrid analog-digital processor may determine, using the output(s), an unbiased estimate of a matrix operation result. The hybrid analog-digital processor may store, in the memory, the unbiased estimate of the matrix operation result encoded in the number format.

An adapter device includes a printed circuit board (PCB), an output port disposed on the PCB and having first pins, where the output port is to be connected to an output harness that is connected to an adaptive device. The adapter also includes wireless circuitry one of disposed on or coupled to the PCB and a processing device disposed on the PCB and coupled to the output port and wireless circuitry. The processing device is to: identify, via the wireless circuitry, an actuation command from a wireless signal received from a handheld electronic device; translate the actuation command to one or more actuation bits that match one of analog-converted bits receivable over an input harness or digital control bits receivable over a wireless controller associated with the adaptive device; and provide the actuation bits to the first pins, the actuation bits causing the adaptive device to perform a specific action.

A method for implementing a matrix operation. A first digital result is determined for the matrix operation as a function of a first analog addition using a first memristor array, a second digital result being determined as a function of a second analog addition using a second memristor array, and the first result and the second result being digitally added. A device for implementing a matrix operation. The device includes at least one first memristor array and one second memristor array, a first analog-to-digital converter and a second analog-to-digital converter. The device is designed to determine a first digital result for the matrix operation as a function of a first analog addition using the first memristor array and of the first analog-to-digital converter, and to determine a second digital result as a function of a second analog addition using the second memristor array and of the second analog-to-digital converter.

A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.

The present disclosure describes a mixed signal arithmetic logic unit configured to use a combination of analog processing elements and digital processing elements in a cohesive manner. Depending on the signals and the data received for processing, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize computational results and the performance of the mixed signal arithmetic logic unit.