In some examples, a device includes a first processing core comprising a resistive memory array to perform an analog computation, and a digital processing core comprising a digital memory programmable with different values to perform different computations responsive to respective different conditions. The device further includes a controller to selectively apply input data to the first processing core and the digital processing core.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

In a hybrid computing system including at least one analog processor and at least one digital processor an embedded problem is repeatedly run or executed on the analog processor(s) to generate a first plurality of candidate solutions to the computational problem, the candidate solutions are returned to the digital processor(s) which determine a value for at least one statistical feature of the candidate solutions, at least one programmable parameter of the plurality of analog devices in the analog processor(s) is adjusted to at least partially compensate for deviations from an expected value of the at least one statistical feature, the expected value of the at least one statistical feature inferred from the structure of the embedded problem, the embedded problem is again repeatedly run or executed on the analog processor(s) to generate a second plurality of candidate solutions to the computational problem.

In a hybrid computing system including at least one analog processor and at least one digital processor an embedded problem is repeatedly run or executed on the analog processor(s) to generate a first plurality of candidate solutions to the computational problem, the candidate solutions are returned to the digital processor(s) which determine a value for at least one statistical feature of the candidate solutions, at least one programmable parameter of the plurality of analog devices in the analog processor(s) is adjusted to at least partially compensate for deviations from an expected value of the at least one statistical feature, the expected value of the at least one statistical feature inferred from the structure of the embedded problem, the embedded problem is again repeatedly run or executed on the analog processor(s) to generate a second plurality of candidate solutions to the computational problem.

A system can include a memristive crossbar array, which can include row lines and column lines intersecting the row lines. Resistive memory elements can be coupled between the row lines and the column lines at the junctions formed by the row and column lines. The resistive memory elements represent the values of the matrix. The system can further include an analogue circuit. The system can be configured to perform an exponentiation of the values of the vector in accordance with a first exponent. The crossbar array can be configured to apply the resulting values of the vector to the resistive elements thereby generating currents. The analogue circuit can be configured to perform an exponentiation of the generated currents in accordance with a second exponent.

In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.

In an example, a method comprises receiving a first matrix of values to be mapped to a resistive memory array, wherein each value in the matrix is to be represented as a resistance of a resistive memory element. An outlying value may be identified in the first matrix. At least one value of a portion of the first matrix containing the outlying value may be substituted with at least one substitute value to form a substituted first matrix.

The disclosure relates to a data processing method, a device, and related products. The related product includes a motherboard comprising a CPU and a board card. The board card comprises multiple artificial intelligence processors. Memories corresponding to the artificial intelligence processors are multi-channel. After receiving an artificial intelligence processor computation instruction sent by a general-purpose processor CPU through a target parallel thread, through a memory channel corresponding to the target parallel thread, a target artificial intelligence processor accesses a physical memory corresponding to the memory channel according to the computation instruction. The target artificial intelligence processor is any of the multiple artificial intelligence processors. The target parallel thread is any of multiple parallel threads started by the CPU. At least two threads in the multiple parallel threads correspond to different memory channels. By adopting the method, user-defined activation functions may run smoothly on an artificial intelligence processor.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.