An apparatus includes a light source to provide a plurality of input optical modes in a squeezed state. The apparatus also includes a network of interconnected reconfigurable beam splitters (RBSs) configured to perform a unitary transformation of the plurality of input optical modes to generate a plurality of output optical modes. An array of photon counting detectors is in optical communication with the network of interconnected RBSs and configured to measure the number of photons in each mode of the plurality of the output optical modes after the unitary transformation. The apparatus also includes a controller operatively coupled to the light source and the network of interconnected RBSs. The controller is configured to control at least one of the squeezing factor of the squeezed state of light, the angle of the unitary transformation, or the phase of the unitary transformation.

Embodiments relate to a method for estimating an amplitude of a unitary operator U to within an error ε by using a quantum processor configurable to implement the unitary operator U on a quantum circuit. The quantum circuit has a maximum depth S can implement the unitary operator no more than D times in a single run. A schedule of iterations n=1 to N based on the error ε and number D is determined. Each iteration n characterized by a schedule parameter kn. kn≤D for all n and kn increases at a rate that is less than exponential. The iterations n may be sequentially executed. In each iteration, the quantum processor is configured to sequentially apply and execute the unitary operator U kn times on the quantum circuit. A non-quantum processor then estimates the amplitude of the unitary operator U based on the measured resulting states.

Embodiments relate to a method for estimating an amplitude of a unitary operator U to within an error ε by using a quantum processor configurable to implement the unitary operator U on a quantum circuit. The quantum circuit has a maximum depth S can implement the unitary operator no more than D times in a single run. A schedule of iterations n=1 to N based on the error ε and number D is determined. Each iteration n characterized by a schedule parameter kn. kn≤D for all n and kn increases at a rate that is less than exponential. The iterations n may be sequentially executed. In each iteration, the quantum processor is configured to sequentially apply and execute the unitary operator U kn times on the quantum circuit. A non-quantum processor then estimates the amplitude of the unitary operator U based on the measured resulting states.

Apparatuses and systems for a die-integrated aspheric mirror are described herein. One apparatus includes an ion trap die including a number of ion locations and an aspheric mirror integrated with the ion trap die.

A qubit system is provided wherein successive sets of M RF pulses are generated simultaneously, for application to qubit circuits in a plurality of N groups of M qubit circuits. M switching multiplexer circuits are used, each to pass a respective one of the M RF pulses in the set to a selected one of a plurality of N M to one RF combiners in a multiplexing mode. Combined RF pulses at M different RF frequencies are transmitted from each of the N combiners to a transmission structure for a respective one of the groups. Individual ones of the combined RF pulses are coupled from the transmission structure for the group to respective ones of the qubit circuits of the groups via respective frequency selective filters. In a broadcast mode the M switching multiplexer circuits are used to transmit the simultaneous pulses to all of RF combiners.

A mixed semiconductor-superconductor platform is fabricated in phases. In a masking phase, a dielectric mask is formed on a substrate, such that the dielectric mask leaves one or more regions of the substrate exposed. In a selective area growth phase, a semiconductor material is selectively grown on the substrate in the one or more exposed regions. In a superconductor growth phase, a layer of superconducting material is formed, at least part of which is in direct contact with the selectively grown semiconductor material. The mixed semiconductor-superconductor platform comprises the selectively grown semiconductor material and the superconducting material in direct contact with the selectively grown semiconductor material.

In one embodiment, a secure computing system comprises a key generation sub-system configured to generate cryptographic keys and corresponding key labels for distribution to computer clusters, each computer cluster including a plurality of respective endpoints, a plurality of quantum key distribution (QKD) devices connected via respective optical fiber connections, and configured to securely distribute the generated cryptographic keys among the computer clusters, and a key orchestration sub-system configured to manage caching of the cryptographic keys in advance of receiving key requests from applications running on ones of the endpoints, and provide respective ones of the cryptographic keys to the applications to enable secure communication among the applications.

In one embodiment, a secure computing system comprises a key generation sub-system configured to generate cryptographic keys and corresponding key labels for distribution to computer clusters, each computer cluster including a plurality of respective endpoints, a plurality of quantum key distribution (QKD) devices connected via respective optical fiber connections, and configured to securely distribute the generated cryptographic keys among the computer clusters, and a key orchestration sub-system configured to manage caching of the cryptographic keys in advance of receiving key requests from applications running on ones of the endpoints, and provide respective ones of the cryptographic keys to the applications to enable secure communication among the applications.

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

The disclosure describes various aspects related to enabling effective multi-qubit operations, and more specifically, to techniques for enabling parallel multi-qubit operations on a universal ion trap quantum computer. In an aspect, a method of performing quantum operations in an ion trap quantum computer or trapped-ion quantum system includes implementing at least two parallel gates of a quantum circuit, each of the at least two parallel gates is a multi-qubit gate, each of the at least two parallel gates is implemented using a different set of ions of a plurality of ions in a ion trap, and the plurality of ions includes four or more ions. The method further includes simultaneously performing operations on the at least two parallel gates as part of the quantum operations. A trapped-ion quantum system and a computer-readable storage medium corresponding to the method described above are also disclosed.