A power supply device is used to provide power to an encryption and decryption device of a security system, including a safety power supply device, which is used to supply the supply voltage according to the system voltage; a regulated voltage source, which is used to provide a regulated voltage; and a voltage selection device, which is electrically connected with the safety power supply device, the stable voltage source and the encryption and decryption device. During the startup period of the security system, or, after the startup period of the security system and the encryption/decryption device performs encryption/decryption, only the supply voltage is selected as the driving voltage of the encryption/decryption device. After the startup period of the security system and the encryption and decryption device does not perform encryption and decryption, the voltage only the regulated voltage is selected as the driving voltage of the encryption and decryption device.

A secure selective product computation system (100) has conditions [c.sub.0], . . . , [c.sub.n−1] and a binary table including m.sub.0,0, m.sub.0,1, . . . , m.sub.n−1,0, and m.sub.n−1, 1 as inputs, and outputs a total product [A] of multipliers selected according to the conditions. A condition integrator (11) calculates share values [c.sub.ic.sub.i+1]. A table convertor (12) generates a 4-value table including m′.sub.00, m′.sub.01, m′.sub.10, and m′.sub.11 A public value multiplier (13) calculates [ai]:=[c.sub.ic.sub.i+1](m.sub.00+m.sub.11−m.sub.01−m.sub.10)+[c.sub.i](m.sub.i+1,0−m.sub.i,0)+[c.sub.i+1](m.sub.i,1−m.sub.i,0)+m.sub.i,0. A real number multiplier (14) calculates a value [A] obtained by multiplying all [a.sub.i]. A selective multiplier (15) multiplies [A] by a multiplier selected from multipliers m.sub.n−1, 0 and m.sub.n−1,1 according to c.sub.n−1 when n is an odd number.

One embodiment provides an apparatus. The apparatus includes a lightweight cryptographic engine (LCE), the LCE is optimized and has an associated throughput greater than or equal to a target throughput.

One embodiment provides an apparatus. The apparatus includes a lightweight cryptographic engine (LCE), the LCE is optimized and has an associated throughput greater than or equal to a target throughput.

Embodiments include systems, methods, computer readable media, and devices configured to, for a first processor of a platform, generate a platform root key; create a data structure to encapsulate the platform root key, the data structure comprising a platform provisioning key and an identification of a registration service; and transmit, on a secure connection, the data structure to the registration service to register the platform root key for the first processor of the platform. Embodiments include systems, methods, computer readable media, and devices configured to store a device certificate received from a key generation facility; receive a manifest from a platform, the manifest comprising an identification of a processor associated with the platform; and validate the processor using a stored device certificate.

Embodiments include systems, methods, computer readable media, and devices configured to, for a first processor of a platform, generate a platform root key; create a data structure to encapsulate the platform root key, the data structure comprising a platform provisioning key and an identification of a registration service; and transmit, on a secure connection, the data structure to the registration service to register the platform root key for the first processor of the platform. Embodiments include systems, methods, computer readable media, and devices configured to store a device certificate received from a key generation facility; receive a manifest from a platform, the manifest comprising an identification of a processor associated with the platform; and validate the processor using a stored device certificate.

A device, system and method for securely executing recursive computations over encrypted data in a homomorphically encrypted (HE) space. For a recursive algorithm with sequentially dependent recursive iterations, executing the recursive algorithm in parallel by computing multiple recursive iterations simultaneously over multiple parallel execution iterations and not in sequential order. Each parallel execution iteration may compute a partial HE solution of multiple sequential recursive iterations comprising a known HE part and leaves empty a placeholder call slot for an unknown HE part. Placeholder call slots remain empty and are filled at delayed times at a later parallel execution iteration from when the known part of the same HE computation is computed. A final HE solution is computed in fewer multiple parallel execution iterations than the number of sequential recursive iterations, thereby accelerating the recursive algorithm in HE space.

An electronic device such as a hardware security module device comprises a first cryptographic processing circuit configured to receive input data packets and apply thereto a first cryptographic processing to provide output data packets. A second cryptographic processing circuit is provided in the device, configured to receive the output data packets, apply thereto a second cryptographic processing inverse to the first cryptographic processing, and provide comparison data packets as a result of applying the second cryptographic processing to the output data packets received. A comparison processing circuit in the device is configured to compare the input data packets with the comparison data packets, and to produce an error signal as a result of the input data packets being different from the comparison data packets.

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.

Fully homomorphic encryption integrated circuit (IC) chips, systems and associated methods are disclosed. In one embodiment, a method of operation for a number theoretic transform (NTT) butterfly circuit is disclosed. The (NTT) butterfly circuit includes a high input word path cross-coupled with a low word path. The high input word path includes a first adder/subtractor, and a first multiplier. The low input word path includes a second adder/subtractor, and a second multiplier. The method includes selectively bypassing the second adder/subtractor and the second multiplier, and reconfiguring the low and high input word paths into different logic processing units in response to different mode control signals.