Patent classifications
G09C1/00
SECRET CALCULATION SYSTEM, SECRET CALCULATION METHOD, AND PROGRAM
A secret calculation system is a secret calculation system that executes secret calculation for calculating data in an encrypted state, and includes a first acquisition unit that acquires first data encrypted, a second acquisition unit that acquires second data unencrypted according to the first data, a secret calculation unit that executes the secret calculation on the basis of the first data and the second data, and an output unit that outputs a result of the secret calculation in an encrypted state. As a result, it is possible to improve data security and reduce a processing load on the secret calculation.
EFFICIENT POST-QUANTUM SECURE SOFTWARE UPDATES TAILORED TO RESOURCE-CONSTRAINED DEVICES
A method comprises receiving an image of an update for a software module, a rate parameter, an index parameter, and a public key, generating a 32-byte aligned string, computing a state parameter using the 32-byte aligned string, generating a modified message representative, computing a Merkle Tree root node, and in response to a determination that the Merkle Tree root node matches the public key, forwarding, to a remote device, the image of the update for a software module, the state parameter; and the modified message representative.
SECRET COMPUTATION SYSTEM, SECRET COMPUTATION SERVER, AUXILIARY SERVER, SECRET COMPUTATION METHOD, AND PROGRAM
In a secret computation system, each of the three or more secret computation servers is configured to transmit, to the auxiliary server, carry computation information for computing a carry indicating whether or not digit carry occurs when a share of arithmetic operation is added as a binary number. The auxiliary server is configured to compute the carry based on the carry computation information received and compute an adjustment value used for computing the share of the arithmetic operation from a share of logical operation by using the computed carry. The auxiliary server distributes the computed adjustment value to the three or more secret computation servers. Each of the three or more secret computation servers is configured to convert the share of the logical operation to the share of the arithmetic operation by using a distributed value of the adjustment value.
DATA ACCESS METHOD, DATA STORAGE SYSTEM, SERVER APPARATUS, CLIENT APPARATUS, AND PROGRAM
A search key is generated (S20). A key relationship array is transmitted (S11). If an element matching the key relationship array is present, the found search key is held (S21). A key relationship index is transmitted (S22). A record read out using the key relationship index is transmitted (S12). If the record matches the search key, the found search key is held (S23). The found search key is set for an empty element of the key relationship array and is transmitted (S24). A data array is transmitted (S13). If an element matching the data array is present, the found data is held (S25). A data index is transmitted (S26). A record read out using the data index is transmitted (S14). If the record matches the search key, the found data is held (S27). Desired data is set for an empty element of the data array and is transmitted (S28).
PHYSICALLY UNCLONABLE FUNCTION DEVICE
A physically unclonable function (PUF) device comprises a plurality of conductors, at least some of which are arranged so that they interact electrically and/or magnetically with one another. A media surrounds at least a portion of each of the conductors, and circuitry is configured for applying an electrical challenge signal to at least one of the conductors and for receiving an electrical output from at least one of the other conductors to generate an identifying response to the challenge signal that is unique to the device. The media comprises a plurality of interactive regions, the interactive regions having an electrical and/or magnetic response characteristic which is permanently altered in response to a predetermined environmental event, and the identifying response is altered with the response characteristic.
Secure public key acceleration
In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.
Secure public key acceleration
In an embodiment, a system is provided in which the private key is managed in hardware and is not visible to software. The system may provide hardware support for public key generation, digital signature generation, encryption/decryption, and large random prime number generation without revealing the private key to software. The private key may thus be more secure than software-based versions. In an embodiment, the private key and the hardware that has access to the private key may be integrated onto the same semiconductor substrate as an integrated circuit (e.g. a system on a chip (SOC)). The private key may not be available outside of the integrated circuit, and thus a nefarious third party faces high hurdles in attempting to obtain the private key.
SECURING CRYPTOGRAPHIC OPERATIONS FROM SIDE CHANNEL ATTACKS USING A CHAOTIC OSCILLATOR
A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.
Encryption and decryption method based on gene chip
A method for asymmetric encryption based on a gene chip includes the steps of (a) obtaining original information in text or image or other form and converting the same into a binary code, and (b) preprocessing the binary code to obtain a binary matrix. In (c), an encryption key is obtained, the encryption key comprising a gene expression solution. In (d), the gene expression solution is placed on a gene chip according to an arrangement and correspondence of the binary matrix.
Encryption and decryption method based on gene chip
A method for asymmetric encryption based on a gene chip includes the steps of (a) obtaining original information in text or image or other form and converting the same into a binary code, and (b) preprocessing the binary code to obtain a binary matrix. In (c), an encryption key is obtained, the encryption key comprising a gene expression solution. In (d), the gene expression solution is placed on a gene chip according to an arrangement and correspondence of the binary matrix.