The present invention reduces a circuit scale of a driving circuit while maintaining a characteristic of the driving circuit. In a driving circuit of the present invention, a transistor (TRc) including a gate electrode, a semiconductor film (HF), and first and second conductive electrodes (S, D) is provided on an upper side of the substrate. The driving circuit further includes a first conductive film (21) provided in a layer lower than the gate electrode, a second conductive film (22) that serves as the gate electrode, and a first capacitor (C1) defined between the first conductive film (21) and the second conductive film (22).

A scan driver and a driving method thereof, in which the scan driver includes a plurality of stages outputting a gate signal in response to clock signals supplied at a first frequency during a driving time of one frame, wherein the plurality of stages are supplied with the clock signals at a second frequency lower than the first frequency during a hold time of the one frame that is separate from the driving time of the one frame.

One or more embodiments of the present disclosure relate to a display device and a gate driving circuit. There is further provided with a synchronization transistor controlled according to a voltage of a Q node of a m-th scan driver (e.g., a second scan driver) and controlling an electrical connection between an output terminal of the n-th light emitting driver and a clock input terminal of the m-th scan driver, so that the rising characteristic and/or the falling characteristic of the light emission signal which is a type of the gate signal can be improved, thereby improving a threshold voltage compensation performance of the driving transistor and the image quality.

An electronic device includes a substrate, a first light emitting unit, a second light emitting unit, a driving transistor, a first emission transistor, and a second emission transistor. The first light emitting unit and the second light emitting unit are disposed on the substrate. The driving transistor is electrically connected to a voltage source. The first emission transistor is electrically connected between the driving transistor and the first light emitting unit. The second emission transistor is electrically connected between the driving transistor and the second light emitting unit.

The electro-optical device includes a plurality of digital scanning lines, a plurality of analog scanning lines, a digital signal line, an analog signal line, and a plurality of pixel circuits. Each of the pixel circuits includes a light emitting element, a digital driving circuit, and an analog driving circuit. The digital driving circuit performs digital driving in which a drive current is supplied to the light emitting element in a period of a length corresponding to a grayscale value. The analog driving circuit performs analog current setting in which a current value of the drive current is set based on an analog data voltage. In a period in which the pixel circuit connected to an s-th digital scanning line and an s-th analog scanning line performs the analog current setting, the pixel circuit connected to a t-th digital scanning line and a t-th analog scanning line performs the digital driving.

A gate driver circuit can include a plurality of stage circuits, in which each of the plurality of stage circuits supplies a gate signal to gate lines arranged in a display panel, and includes an M node, a Q1 node, a Q2 node, a QB node, a line selector, a Q1 node controller, a Q1 node stabilizer, an inverter, a QB node stabilizer, a carry signal output circuit portion, and a gate signal output circuit portion, in which a first low-potential voltage level, a third low-potential voltage level, and a fourth low-potential voltage level for operating the gate driver circuit are set to different values, and the gate driver circuit can have a reduced size and better prevent leakage current while also providing more stable gate signals.

A micro-LED display having a plurality of pixels arranged in a two-dimensional matrix, wherein an individual pixel of the plurality of pixels each includes a light-emission section and a drive circuit to drive the light-emission section. The drive section includes an in-pixel PWM circuitry to receive a sawtooth or triangular pulse and an electric potential based on an image signal voltage, and to output a current pulse based on a comparison of the sawtooth or triangular pulse and the electric potential. The in-pixel PWM circuitry includes at most 7 transistors. The micro-LED display includes is coupled to one or more circuitries coupled to the plurality of pixels to provide the sawtooth or triangular pulse and the electric potential.

A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

A display panel includes a second display region and a first display region which are arranged side by side in a direction in which data signal lines extend, and a source driver is provided at one edge of the second display region. Switches are provided between data signal lines in the first display region and data signal lines in the second display region, and the switches are turned off when an on-level scanning signal is applied to a scanning signal line in the second display region. A period during which the on-level scanning signal is applied to each scanning signal line in the second display region is shorter than a period during which the on-level scanning signal is applied to each scanning signal line in the first display region.

A display panel and a display device are provided. The display panel includes a pixel circuit including a driving module, a first reset module, a compensation module, a light-emitting control module and a light-emitting module. The first reset module includes a first dual-gate transistor, and the compensation module includes a second dual-gate transistor. A first intermediate node of the first dual-gate transistor and a second intermediate node of the second dual-gate transistor are electrically connected to a light-emitting control signal line through a first capacitor and a second capacitor, respectively. The first dual-gate transistor includes a first parasitic capacitor corresponding to the first capacitor, and the second dual-gate transistor includes a second parasitic capacitor corresponding to the second capacitor. A capacitance of at least one of the first capacitor and the second capacitor is greater than or equal to a capacitance of the corresponding parasitic capacitor.