Patent classifications
G09G2230/00
GATE DRIVER AND DISPLAY DEVICE USING THE SAME
A gate driver according to an embodiment and a display device using the same are discussed. The gate driver can output a gate signal to a pixel circuit having a driving element connected between a first power line and a first node, a light-emitting element connected between the first node and a second power line, and a switching element connected between the first node and a third power line and driven by the gate signal. The gate driver includes a first circuit unit to receive a carry signal from a previous signal transmission unit to charge or discharge a first control node and a second control node, and a second circuit unit having a first buffer transistor and a second buffer transistor configured to output the gate signal based on a first clock signal and a first low potential voltage according to potentials of the first and second control nodes.
PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME
A pixel circuit of a display device includes a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and configured to supply an electric current to a light-emitting element; a first switch element configured to be turned on according to a gate-on voltage and supply a data voltage to the second node; a first capacitor connected between the second node and the third node; a second capacitor connected between the third node and the fourth node; and a third capacitor connected between the fourth node and the first node, or between the fourth node and a power line to which the pixel driving voltage is applied.
Light Emitting Display Device And Driving Method Thereof
A light emitting display device is disclosed that includes an organic light emitting diode having an anode electrode connected to a first power line and a cathode electrode, a capacitor configured to store a data voltage and having a first electrode and a second electrode, and a driving transistor having a first electrode connected to the cathode electrode of the organic light emitting diode, a gate electrode connected to the first electrode of the capacitor, and a second electrode connected to the second electrode of the capacitor and a second power line. The driving transistor applies an initialization voltage to a node connected to the cathode electrode of the organic light emitting diode and the first electrode of the driving transistor.
Scan driver and driving method thereof
A scan driver and a driving method thereof, in which the scan driver includes a plurality of stages outputting an output signal in response to clock signals supplied at a first frequency during a driving time of one frame, wherein the plurality of stages are supplied with the clock signals at a second frequency lower than the first frequency during a hold time of the one frame that is separate from the driving time of the one frame.
COORDINATED TOP ELECTRODE - DRIVE ELECTRODE VOLTAGES FOR SWITCHING OPTICAL STATE OF ELECTROPHORETIC DISPLAYS USING POSITIVE AND NEGATIVE VOLTAGES OF DIFFERENT MAGNITUDES
A system for simplified driving of electrophoretic media using a positive and a negative voltage source, where the voltage sources have different magnitudes, and a controller that cycles the top electrode between the two voltage sources and ground while coordinating driving at least two drive electrodes opposed to the top electrode. The resulting system can achieve roughly the same color states as compared to supplying each drive electrode with six independent drive levels and ground. Thus, the system simplifies the required electronics with only marginal loss in color gamut. The system is particularly useful for addressing an electrophoretic medium including four sets of different particles, e.g., wherein three of the particles are colored and subtractive and one of the particles is light-scattering.
Methods for driving electro-optic displays
An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme.
Display Apparatus and Electronic Device
A display apparatus with high display quality is provided. A high-resolution display apparatus is provided. The display apparatus includes a plurality of pixels, and the pixels each include a light-emitting device, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor. One electrode of the light-emitting device is electrically connected to one of a source and a drain of the first transistor, one of a source and a drain of the second transistor, and one electrode of the first capacitor. A gate of the second transistor is electrically connected to the other electrode of the first capacitor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor. One frame period of each of the pixels includes a period in which the first transistor and the fourth transistor are each in a conduction state.
SHIFT REGISTER, GATE DRIVE CIRCUIT AND DRIVE METHOD THEREOF
A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.
DISPLAY PANEL AND ELECTRONIC DEVICE
According to one embodiment, a display panel includes scanning lines, signal lines, a pixel switching element, a pixel electrode, and a first control switch including first control switching elements. Each of the first control switching elements is composed of a transistor and includes a gate electrode, a source electrode, and a drain electrode. The scanning lines electrically connected to the gate electrodes of the first control switching elements are different from each other. The drain electrodes of the first control switching elements are electrically bundled and are connected to power source voltage output terminal of the first control switch.
Gate driver circuit, display device and driving method
A gate driver circuit, a display device and a driving method. The gate driver circuit includes: a scan signal generation circuit, wherein the scan signal generation circuit includes N1 stages of first output terminals, and the scan signal generation circuit is configured to output N1 first pulse scan signals stage by stage respectively through the N1 stages of first output terminals; and N2 level conversion circuits, wherein the N2 level conversion circuits are configured to output under a control of a plurality of conversion control signals N1 second pulse scan signals which are in one-to-one correspondence with the N1 first pulse scan signals, and the plurality of conversion control signals include a plurality of first sub-control signals which are the N1 first pulse scan signals, wherein N1 is an integer greater than or equal to 2, and N2 is an integer greater than or equal to 2.