To provide a semiconductor device, a liquid crystal display device, and an electronic device which have a wide viewing angle and in which the number of manufacturing steps, the number of masks, and manufacturing cost are reduced compared with a conventional one. The liquid crystal display device includes a first electrode formed over an entire surface of one side of a substrate; a first insulating film formed over the first electrode; a thin film transistor formed over the first insulating film; a second insulating film formed over the thin film transistor; a second electrode formed over the second insulating film and having a plurality of openings; and a liquid crystal over the second electrode. The liquid crystal is controlled by an electric field between the first electrode and the second electrode.

An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

A display driving device, a control method therefor, and a display apparatus. The control method comprises: a main processing chip generates a read-write synchronization signal when buffering received display data, and each secondary processing chip receives the read-write synchronization signal (S202); in response to the read-write synchronization signal, the main processing chip buffers the received display data of the current frame image to be displayed to the frame address of a corresponding memory, and performs reading and processing on the buffered display data of a previous frame image to be displayed and then transmits to a display panel, and in response to the read-write synchronization signal, each secondary processing chip synchronously buffers the received display data of the current frame image to be displayed to the frame address of the corresponding memory, and synchronously performs reading and processing on the buffered display data of the previous frame image to be displayed and then transmits to the display panel (S203). By means of the read-write synchronization signal, the main processing chip and all the secondary processing chips are controlled to control the storage and read operations of the memory, and thus, the present invention can avoid that the processing chips share the frame address of the memory, and further can avoid the problem of abnormal image display due to multiple asynchronous processing chips.

A display controller is provided. The display controller includes n field-programmable gate arrays (FPGAs) (n is an integer greater than 1). A respective one of the n FPGAs includes a first input circuit and an output circuit and a first process circuit connected between the first input circuit and the output circuit. The first input circuit is configured to receive a respective one first sub-image corresponding to the respective one of the n FPGAs. The n first sub-images are combined to form one frame of initial image. The first process circuit is configured to enhance image-resolution of the respective one first sub-image to obtain a respective one second sub-image and the output circuit is configured to deliver the respective one second sub-image corresponding to the respective one of the n FPGAs to a timing-controller.

A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.

An image processing device and image processing method that reduce the probability that the power consumption of two processing systems will be maximized simultaneously. Such image processing device includes an image processing circuit, a conversion circuit receiving a first pixel data array outputted from the image processing circuit and converting the first pixel data array into a second pixel data array by converting an arrangement of pieces of pixel data included in the first pixel data array pixel by pixel, the first pixel data array being an aggregate of a plurality of pieces of pixel data, the pieces of pixel data being pieces of data corresponding to a plurality of pixels, each of the pieces of pixel data having a plurality of bits, an aggregate of the pixels forming a pixel array, and a processing unit processing the second pixel data array outputted from the conversion circuit.

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

The disclosure describes aspects of a display processing circuitry. In an aspect, one or more displays that support multiple views include one or more arrays of pixels, one or more backplanes, and a processing circuitry configured to receive one or more data streams, control processing of the data streams based on policies from which to select a mode of operation, each mode of operation defining which rays of light the arrays of pixels in the displays are to contribute to generate a particular view or views and the tasks to be performed by the processing circuitry to modify the data streams accordingly. The processing circuitry further provides signaling representative of the modified data streams to the arrays of pixels through a circuit configuration of the backplanes for the arrays of pixels to contribute the rays that will to generate the particular view or views. A corresponding method is also described.

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.