An image output apparatus according to the present invention includes: communicating units; an acquiring unit configured to acquire, for each of the communicating unit connected to an image display apparatus, correspondence information; a setting unit configured to set, for each of the communicating unit, an output mode; and an outputting unit configured to output, for each of the communicating unit, image data based on an output mode set with respect to the communicating unit, wherein the setting unit automatically sets a first output mode with respect to a communicating unit for which the correspondence information has been acquired.

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.

A display controller is provided. The display controller includes n field-programmable gate arrays (FPGAs) (n is an integer greater than 1). A respective one of the n FPGAs includes a first input circuit and an output circuit and a first process circuit connected between the first input circuit and the output circuit. The first input circuit is configured to receive a respective one first sub-image corresponding to the respective one of the n FPGAs. The n first sub-images are combined to form one frame of initial image. The first process circuit is configured to enhance image-resolution of the respective one first sub-image to obtain a respective one second sub-image and the output circuit is configured to deliver the respective one second sub-image corresponding to the respective one of the n FPGAs to a timing-controller.

Video or graphics, received by a render engine within a graphics processing unit, may be segmented into a region of interest such as foreground and a region of less interest such as background. In other embodiments, an object of interest may be segmented from the rest of the depiction in a case of a video game or graphics processing workload. Each of the segmented portions of a frame may themselves make up a separate surface which is sent separately from the render engine to the display engine of a graphics processing unit. In one embodiment, the display engine combines the two surfaces and sends them over a display link to a display panel. The display controller in the display panel displays the combined frame. The combined frame is stored in a buffer and refreshed periodically. In accordance with another embodiment, video or graphics may be segmented by a render engine into regions of interest or objects of interest and objects not of interest and again each of the separate regions or objects may be transferred to the display engine as a separate surface. Then the display engine may transfer the separate surfaces to a display controller of a display panel over a display link. At the display panel, a separate frame buffer may be used for each of the separate surfaces.

Systems and methods for super sampling and viewport shifting of non-real time 3D applications are disclosed. In one embodiment, a graphics processing unit includes a processing resource to execute graphics commands to provide graphics for an application, a capture tool to capture the graphics commands, and a data generator to generate a dataset including at least one frame based on the captured graphics commands and to modify viewport settings for each frame of interest to generate a conditioned dataset.

A method and system are configured to generate user-specific information, such as wager-related information, for display on one or more display devices of a user. The system is configured to use factors, such as user preferences, user activity information, user location, user group information and/or a configuration of the user's display device(s), to generate, from a set of wager-related information such as a set of available bets, the user-specific information, such as a specific sub-set of the information or bets.

An information processing apparatus includes a generation unit and an instruction unit. The generation unit generates a display image including information on speech or action of a target person, based on history information that the target person has made speech or action. The instruction unit instructs a display device, which displays an image of a virtual space so as to be superimposed in a real space, to display the generated display image as the image of the virtual space.

A processing system synchronizes the frequencies and phases of the display outputs of multiple video processing units (VPUs) by adjusting a local time base generated at each VPU to match a virtual global time base generated based on a network protocol and to synchronize video timing for the display outputs based on the virtual global time base.

To provide a semiconductor device, a liquid crystal display device, and an electronic device which have a wide viewing angle and in which the number of manufacturing steps, the number of masks, and manufacturing cost are reduced compared with a conventional one. The liquid crystal display device includes a first electrode formed over an entire surface of one side of a substrate; a first insulating film formed over the first electrode; a thin film transistor formed over the first insulating film; a second insulating film formed over the thin film transistor; a second electrode formed over the second insulating film and having a plurality of openings; and a liquid crystal over the second electrode. The liquid crystal is controlled by an electric field between the first electrode and the second electrode.

It is an object to provide a display device which can favorably display a image without delayed or distorted signals. The display device includes a first gate driver and a second gate driver. The first gate driver and the second gate driver each include a plurality of flip flop circuits and a plurality of transfer signal generation circuits. Both the flip flop circuit and the transfer signal generation circuit are circuits which output a signal inputted to a first input terminal with a half clock cycle delay. In addition, an output terminal of the transfer signal generation circuit is directly connected to a first input terminal of the flip flop circuit in the next stage. Therefore, delay and distortion of the signal which is inputted from the transfer signal generation circuit to the flip flop circuit can be reduced.