A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

A solid-state drive device includes a memory module in which at least one non-volatile memory device is mounted, a first heat storage unit and a second heat storage unit covering upper and lower parts of the memory module, respectively, to store heat emitted by the memory module, and having at least portions connected to each other, respectively, a cover having a space in which the memory module and the first and second heat storage units are received and arranged with a spacing distance from the first and second heat storage units, respectively, and an inner frame arranged between the cover and at least one of the first and second heat storage units, to provide the spacing distance.

One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

The present invention discloses a first preferred processor comprising a fixed look-up table circuit (LTC) and a writable LTC. The fixed LTC realizes at least a common function while the writable LTC realizes at least a non-common function. The present invention further discloses a second preferred processor comprising a two-dimensional (2-D) LTC and a three-dimensional (3-D) LTC. The 2-D LTC realizes at least a fast function while the 3-D LTC realizes at least a non-fast function.

According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

A semiconductor device includes a buffer control circuit suitable for generating a buffer control signal in response to a power-down mode signal and a detection pulse, a first buffer circuit suitable for generating a first internal chip select signal by buffering a chip select signal depending on a select signal which is generated in response to the buffer control signal in a power-down mode, and a detection pulse generation circuit suitable for generating the detection pulse in response to the first internal chip select signal.

An electronic apparatus includes a base that includes a flat portion and a side wall provided upright on a part of an outer edge of the flat portion, a printed circuit board disposed in the base and including a device, and a cover covering the base. The base includes a hole that is contiguous to the side wall and provided in the flat portion, a support portion, one end of the support portion being supported by the side wall, and a positioning member provided on the support portion and positioning the cover with respect to the base.

An electronic apparatus includes a base that includes a flat portion and a side wall provided upright on a part of an outer edge of the flat portion, a printed circuit board disposed in the base and including a device, and a cover covering the base. The base includes a hole that is contiguous to the side wall and provided in the flat portion, a support portion, one end of the support portion being supported by the side wall, and a positioning member provided on the support portion and positioning the cover with respect to the base.

Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.