A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

An integrated circuit is provided that includes memory elements that exhibit immunity to soft error upset (SEU) events when subjected to high-energy atomic particle strikes. Each memory element may include at least two inverting circuits coupled in a feedback loop. Transistors in the memory element may be grouped in one contiguous region or divided into multiple separate regions. The memory element may include a long gate conductor that extends outside the boundary of the one contiguous region or the multiple separated regions. The long gate conductor may serve to provide parasitic resistance in the feedback loop to help mitigate SEU disturbances.

A memory subsystem is operable with a memory controller of a host computer system via an interface. The memory subsystem comprises dynamic random access memory elements and a memory subsystem controller. The memory subsystem controller has an open drain output, and is configured to provide a first signaling interface via the open drain output during normal operations and a second signaling interface via the open drain output during an initialization operation. The second signaling interface is distinct from the first signaling interface and the initialization operation is distinct from any of the normal operations. The first signaling interface is used by the memory subsystem controller to indicate a parity error in response to a parity error having occurred during the normal operations. The second signaling interface is used by the memory subsystem controller to output a signal related to initialization operation sequences during the initialization operation.

A data line control circuit has a data line driving circuit and a write-assist data line driving circuit. The data line driving circuit is used to drive differential data lines during a write operation of at least one memory cell. The write-assist data line driving circuit is used to drive at least one write-assist data line during the write operation of the at least one memory cell, wherein the at least one write-assist data line is isolated from the differential data lines, and is driven to have a first voltage transition from a first voltage level to a second voltage level, such that one of the differential data lines has a second voltage transition from a third voltage level to a fourth voltage level that is induced by the first voltage transition via capacitive coupling.

A memory device may include a memory cell array including a plurality of memory cells, and an internal operation circuit configured to perform a test operation in a test mode using a parallel bit operation of simultaneously comparing a plurality of bits and also perform an internal operation including a comparison operation with respect to external data in a normal mode other than the test mode using the parallel bit operation.

One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Devices and techniques for NAND cell encoding to improve data integrity are disclosed herein. A high-temperature indicator is obtained and a write operation is received. The write operation is then performed on a NAND cell using a modified encoding in response to the high-temperature indicator. The modified encoding includes a reduced number of voltage distribution positions from an unmodified encoding without changing voltage distribution widths, where each voltage distribution corresponds to a discrete set of states an encoding.

A method for communicating with memory, performed by a memory controller, is provided. The method includes sampling reads from a plurality of memory devices and storing first calibration points in first buffers, based on the sampling, with at least one first calibration point and corresponding first buffer for each of the plurality of memory devices. The method includes sampling a read from a second memory device in background while performing a read from a first memory device using the first calibration point in the first buffer corresponding to the first memory device. The method includes storing a second calibration point in a second buffer, for the second memory device, based on the sampling in the background, with the first buffer for the second memory device having the first calibration point used for ongoing reads of the second memory device.

Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.

Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.