Memory systems are disclosed. A memory system may include a plurality of memory devices and a controller in communication with the plurality of memory devices. The controller may be configured to load respective select information to at least some memory devices of the plurality of memory devices. Each memory device of the at least some memory devices may be configured to store its respective select information. Further, each memory device of the at least some memory devices may be configured to adjust, based on the stored select information and in response to receipt of a signal at the memory device, an impedance characteristic of the memory device during at least a portion of a memory device operation of another memory device of the plurality of memory devices. Associated methods and devices are also disclosed.

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.

A secondary memory device includes: a substrate and a housing configured to accommodate at least a part of the substrate. The substrate has upper and lower opposed surfaces and includes a first region in which a first semiconductor device is mounted on the upper surface and a second region in which a second semiconductor device is mounted on the upper surface. The housing includes a first sub-housing covering the upper surface of the substrate at the first region and the first semiconductor device. The first sub-housing does not extend to cover the upper surface of the substrate at the second region.

Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.

In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time period as indicated by the average amount of power sensed by the sensor over the time period.

A radiation upset detector is provided. The radiation upset detector includes at least one radiation sensitive memory initialized with at least one respective known-signature word; and at least one radiation hardened logic circuitry communicatively coupled to the at radiation sensitive memory to check the known-signature word at at least a kHz rate to detects errors. Responsive to detecting an error in the known-signature word in the radiation sensitive memory, the radiation hardened logic circuitry sends an action command. At least one of: a memory size of the memory; a number of circuits in the logic circuitry; a clock rate for the checking the known-signature word; and at least one corruption threshold is selected based on system reliability requirements of the protected system including at least one of: an overall operational reliability requirement of the protected system; a probability of detection success; false alarm rates; and a required speed of detection.

Embodiments herein describe a multiple die system that includes an interposer that connects a first die to a second die. Each die has a bump interface structure that is connected to the other structure using traces in the interposer. However, the bump interface structures may have different orientations relative to each other, or one of the interface structures defines fewer signals than the other. Directly connecting the corresponding signals defined by the structures to each other may be impossible to do in the interposer, or make the interposer too costly. Instead, the embodiments here simplify routing in the interposer by connecting the signals in the bump interface structures in a way that simplifies the routing but jumbles the signals. The jumbled signals can then be corrected using reordering circuitry in the dies (e.g., in the link layer and physical layer).

Apparatus might include a first plurality of signal lines, a second plurality of signal lines, a controller, a first die, and a second die. The controller, the first die, and the second die might each be connected to the first plurality of signal lines and connected to the second plurality of signal lines. The first die and the second die might each include termination circuitry connected to a particular signal line of the second plurality of signal lines. The first die might be configured to activate its termination circuitry in response to receiving a particular combination of signal values on the first plurality of signal lines. The second die might be configured to deactivate its termination circuitry in response to receiving the particular combination of signal values on the first plurality of signal lines.