Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.

Memory devices might include an input/output (I/O) node, a termination device, an array of memory cells in communication with the I/O node through the termination device, and control circuitry, wherein the control circuitry is configured to compare an address received by the memory device to a plurality of instances of address information stored in the memory device. Each instance of address information of the plurality of instances of address information might correspond to a respective termination value stored in the memory device. In response to the memory device receiving an address matching an instance of address information stored in the memory device, the control circuitry might further be configured to activate the termination device using the respective termination value corresponding to the instance of address information matching the received address.

A memory system includes a memory device including plural memory blocks divided into a system region, a user data region and a reserved region. The system region includes a first block storing original firmware and a second block storing copied firmware, and the reserved region includes a dedicated test block having an operational characteristic that substantially the same as that of the second block. The memory system includes a controller configured to access the dedicated test block for determining a status of the second block based on an operation state of the dedicated test block, and to update both the dedicated test block and the second block based on the status of the second block.

A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

Some embodiments include an integrated assembly having digit lines supported by a base and extending along a first direction. A shield-connection-line is supported by the base and extends along the first direction. Transistor active regions are over the digit lines. Each of the active regions includes a channel region between an upper source/drain region and a lower source/drain region. The lower source/drain regions are coupled with the digit lines. Capacitors are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines extend along the second direction. The shield lines are above the digit lines and are coupled with the shield-connection-line.

A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.

A data storage circuit for storing data from volatile memory in response to a power loss, the data storage circuit including an input for receiving a power loss signal in response to a power loss from at least one power source, an input configured to receive data from a volatile memory, a single block of non-volatile matrix of memory cells and a driver circuit coupled to said single row of non-volatile matrix of memory cells. The driver circuit is configured to write data to and read data from said single block of non-volatile matrix of memory cells. The single block of non-volatile matrix of memory cells can be provided as a single row electrically erasable programmable read only memory (EEPROM).

A solid-state drive device includes a memory module in which at least one non-volatile memory device is mounted, a first heat storage unit and a second heat storage unit covering upper and lower parts of the memory module, respectively, to store heat emitted by the memory module, and having at least portions connected to each other, respectively, a cover having a space in which the memory module and the first and second heat storage units are received and arranged with a spacing distance from the first and second heat storage units, respectively, and an inner frame arranged between the cover and at least one of the first and second heat storage units, to provide the spacing distance.

An integrated circuit including a signal line layout is disclosed. A signal line layout may include a number of signal lines configured for conveying a number of signals. The signal line layout may further include a number of shield lines. Each signal line of the number of signal lines may be positioned adjacent a first shield line and a second shield line of the number of the shield lines. Further, first shield line may extend a length of an adjacent signal line and the second shield line may extend less than a length of the adjacent signal line. An electronic system including circuitry having one or more signal line layouts, and methods of forming signal line layout are also described.

A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.