A memory device includes an address generation circuit, an address processing circuit and a refresh control circuit. The address generation circuit generates a first intermediate address according to a row address. The first intermediate address includes a first wordline address and an identification code indicating whether a first wordline indicated by the first wordline address is a normal or redundant wordline. The address processing circuit refers to the first intermediate address to generate a second intermediate address indicating a second wordline adjacent to the first wordline. The second intermediate address includes a second wordline address and an identification code indicating whether the second wordline is a normal or redundant wordline. The refresh control circuit determines a disturbance count of the second wordline each time the first wordline is activated, and refers to the disturbance count to determine whether to output the second wordline address to refresh the second wordline.

A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value. Increasing set pulses may be applied to memristor while the gate is held at the determined gate voltage.

A set procedure of a one transistor, one memristor memory elements may comprise determining a gate voltage for the transistor based on the desired target value. Increasing set pulses may be applied to memristor while the gate is held at the determined gate voltage.

A method for programming three page user data in a memory array of a non-volatile memory system, comprising converting each three-bit value data pattern of the user data into a representative pair of two-bit data values, simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings, and simultaneously programming two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings.

Techniques are provided for basic input/output system (BIOS) protection using multi-factor authentication (MFA) based on digital identity values. One method comprises obtaining, by a BIOS of a hardware device, from a user device, (i) a request to access the BIOS, and (ii) a token based on a digital identity value for the user device; providing the token to an MFA chip on the hardware device, wherein the MFA chip evaluates the token and provides a verification result to the BIOS; and allowing the user device to access the BIOS based on the verification result. The digital identity value for the user device may be stored by the MFA chip during a fabrication of the MFA chip and/or a registration of the user device. The MFA chip may compare the digital identity value from the token received from the BIOS with the digital identity value for the user device stored by the MFA chip.

A memory includes a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines, a second cell array configured to include a plurality of second memory cells connected to the plurality of word lines, wherein a group of the plurality of second memory cells which are connected to a corresponding word line stores the number of activations for the corresponding word line, and an activation number update unit configured to update a value stored in the corresponding group of the plurality of second memory cells connected to the activated word line of the plurality of word lines.

A memory system including a plurality of dynamic random access memory (DRAM) devices and a DRAM controller is provided. The plurality of DRAM devices includes one or more DRAM groups. Each of the one or more DRAM groups includes at least two DRAM devices. The DRAM controller outputs a clock enable signal, and controls a selection signal used to select a target DRAM device that operates in a normal mode in response to the clock enable signal. At least one target DRAM device is selected from the one or more DRAM groups. One or more stand-by DRAM devices other than the at least one target DRAM device operates in a self-refresh mode.

Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.

A read-amplifier circuit includes a core with a first input and a second input that are intended to receive in a measurement phase a differential signal arising from a first bit line and from a second bit line of the memory device. The circuit also includes a memory element with two inverters coupled in a crossed manner. The first and second inputs are respectively connected to two of the power supply nodes of the inverters via two transfer capacitors. A first controllable circuit is configured to temporarily render the memory element floating during an initial phase preceding the measurement phase and during the measurement phase.

A memory driving device, comprising a switch, a voltage setting circuit, and a bias control circuit. The switch is coupled to a memory at a node. The voltage setting circuit is coupled to the switch and configured to provide a set signal during a first period to turn on the switch, so as to generate current flowing through the switch to the memory unit. The bias control circuit is respectively coupled to the switch and the node, and, during a second period, continuously provides a bias signal to control the switch so as to adaptively adjust a value of the setting current of the switch. The configuration setting terminal is coupled to the voltage setting circuit and the bias control circuit to control the first and the second period.