Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Within a memory 2 comprising an array 4 of bit cells 6 write driver circuitry 14 uses a boosted write signal which is boosted to a lower than normal level during a write operation. Column select transistors 16 are driven by column select circuitry 12. The column select signal is boosted to a lower than normal level when a column is unselected and to higher than a normal level when a column is selected. Voltage boost circuitry, such as charge pumps 20, 22 are employed within the column select circuitry 12 to achieve these boosted levels for the columns select signal.

Apparatuses and methods for performing logical operations using sensing circuitry are disclosed. An apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry.

A wearable computing device is authenticated using bone conduction. When a user wears the device, a bone conduction speaker and a bone conduction microphone on the device contact the user's head at positions proximate the user's skull. A calibration process is performed by transmitting a signal from the speaker through the skull and receiving a calibration signal at the microphone. An authentication process is subsequently performed by transmitting another signal from the speaker through the skull and an authentication signal is received at the microphone. In the event that frequency response characteristics of the authentication signal match the frequency response characteristics of the calibration signal, the user is authenticated and the device is enabled for user interaction without requiring the user to input any additional data.

A semiconductor memory device includes a memory cell array, and a voltage generator suitable for generating voltages supplied to the memory cell array. The memory cell array includes cell strings each including memory cells extending in a first direction and arranged in a second direction and a third direction; bit lines extending in the second direction and electrically coupled to the cell strings; and word lines extending in the third direction and electrically coupled to corresponding memory cells, wherein the word lines includes dummy word lines. A program voltage is supplied to a program word line that is electrically coupled to a memory cell to be programmed, and a level of a first dummy word line voltage supplied to a parallel dummy word line, which is disposed parallel to the program word line in the first direction is different from a level of a second dummy voltage supplied to a nonparallel dummy word line other than the parallel dummy word line.

A refresh control device may include a plurality of latch circuits configured to receive an active signal, a refresh signal, an active control signal, and a refresh control signal, and output a word line enable signal for controlling a refresh operation to banks. The refresh control device may include a command decoder configured to decode a row address in correspondence to an external command signal and generate the active signal and the refresh signal. The refresh control device may include an address buffer configured to buffer an active address and generate the active control signal. The refresh control device may include an address control circuit configured to generate the refresh control signal in correspondence to a refresh command signal.

A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.

A semiconductor device may be provided. The semiconductor device may include an error correction control circuit and a signal storage circuit. The error correction control circuit may be configured to generates first to (P+1).sup.th write parity signals from first to M.sup.th write data signals based on a test mode signal and a read/write signal. Each of the first to (P+1).sup.th write parity signals may be generated by performing a logical operation on at least two write data signals of the first to M.sup.th write data signals. The signal storage circuit may be configured to store the first to M.sup.th write data signals and the first to (P+1).sup.th write parity signals based on the read/write signal.

A semiconductor device may be provided. The semiconductor device may include an error correction control circuit and a signal storage circuit. The error correction control circuit may be configured to generates first to (P+1).sup.th write parity signals from first to M.sup.th write data signals based on a test mode signal and a read/write signal. Each of the first to (P+1).sup.th write parity signals may be generated by performing a logical operation on at least two write data signals of the first to M.sup.th write data signals. The signal storage circuit may be configured to store the first to M.sup.th write data signals and the first to (P+1).sup.th write parity signals based on the read/write signal.

Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.