A method of storing information using monomers such as nucleotides is provided including converting a format of information into a plurality of bit sequences of a bit stream with each having a corresponding bit barcode, converting the plurality of bit sequences to a plurality of corresponding oligonucleotide sequences using one bit per base encoding, synthesizing the plurality of corresponding oligonucleotide sequences on a substrate having a plurality of reaction locations, and storing the synthesized plurality of corresponding oligonucleotide sequences.

Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

A semiconductor device includes a level conversion circuit. The level conversion circuit includes a first transistor, a second transistor, a current limiting element, and a voltage adjusting circuit. The first transistor includes a gate connected to an input node. A signal corresponding to a first power supply voltage is input to the input node. The second transistor has a source connected to a drain of the first transistor, a drain connected to a second power supply voltage that is higher than the first power supply voltage, and a gate connected to a first node. The current limiting element is electrically connected between the first node and an output node. The voltage adjusting circuit adjusts a voltage of the first node in accordance with the signal input to the input node.

The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising respective sense amplifiers and compute components and a controller. The controller may be configured to cause replication of a data value stored in a first compute component such that the data value is propagated to a second compute component.

A nonvolatile memory device includes a memory cell array and an computation output circuit. The memory cell array includes a plurality of nonvolatile memory elements configured to store a plurality of weights respectively and a plurality of bit lines coupled to the plurality of nonvolatile memory elements according to a plurality of input signals. The computation output circuit is configured to generate a computation signal from voltages induced at the plurality of bit lines according to the plurality of input signals.

A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.

Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction (MTJ) for storing data may include a reference layer. A free layer of an MTJ may be separated from a reference layer by a barrier layer. A free layer may be configured such that one or more resistance states for an MTJ correspond to one or more positions of a magnetic domain wall within the free layer. A domain stabilization layer may be coupled to a portion of a free layer, and may be configured to prevent migration of a domain wall into the portion of the free layer.

A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.

A memory device includes a memory cell array having a plurality of memory cell strings, and a plurality of bit lines connected to at least one of the plurality of memory cell strings; and a plurality of page buffers connected to the plurality of bit lines, wherein each of the plurality of page buffers includes a plurality of latches sharing one data transfer node and exchanging data with each other through the data transfer node; and a pass transistor setting a connection between the data transfer node and another data transfer node of another page buffer.