A memory device includes a cell array including cells, an address transition detector outputting a transition detection signal as to whether an address of a write command is changed, and a control logic circuit generating one of word-line-on signals for performing a write operation on the cell array in response to the write command, and terminating the write operation in accordance with the transition detection signal. The word-line-on signals include a long-kept word-line-on signal that stays active before the address is changed and a divided word-line-on signal that is, before the address is changed, divided into sub-word-line-on signals.

A signal generator includes N stages of cascaded control signal generating circuits, and is configured to receive K clock signals whose valid pulse edges are different from each other by a set time, an n-th control signal generating circuit of the N stages of control signal generating circuit generates a strobe signal based on a k-th clock signal of the K clock signals and sequentially outputs at least two different clock signals of other K−1 clock signals based on the strobe signal. A valid pulse edge of the k-th clock signal is within a valid pulse duration of a strobe signal of an (n−1)-th stage control signal generating circuit.

Methods, systems, and devices for delay calibration oscillators for a memory device are described. In some examples, a memory device may include a delay chain operable (e.g., for a calibration operation) in a ring oscillator configuration that includes a pulse generator. The pulse generator may be configured to output a pulse signal responsive to a transition of an input signal. By generating a pulse signal in a feedback loop of a ring oscillator, the ring oscillator may support a cycle that does not rely on both a first transition propagation pass (e.g., a rising edge propagation) and a responsive, opposite transition propagation pass (e.g., a falling edge propagation) through the delay chain, which may support a ring oscillator cycle time (e.g., period) that more closely represents aspects of the delay chain that are meant to be calibrated.

A method includes receiving a first and a second data from a first and second IO pad on a first and second data lines respectively. A data strobe is received from a third IO pad on a data strobe line. The first data and the second data are strobed based on the data strobe to generate a first and second strobed data. The first data from the first IO is received at the data strobe line and strobed based on the data strobe to form an another first strobed data and compared to the first strobed data to generate a comparison signal indicating whether adjustment to a delay of the first data line is needed. A delay command is generated to increase/decrease the delay of the first and second data line.

Methods, systems, and devices for a decoder are described. The memory device may include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder may include a doped material that may extend between a first conductive line and an access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate) and the doped material may be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. The access line may be coupled with two decoders, in some cases.

Provided is a method for operating an interface circuit of a memory device. The method includes receiving a command from a controller; determining whether the command is for a semiconductor memory or the interface circuit, the semiconductor memory operatively coupled to the interface circuit; and when it is determined that the command is for the interface circuit, performing a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performing an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

A memory controller includes a mapping data controller configured to generate extended mapping data including mapping information and an additional field in response to an extended mapping data request received from a host and to generate data generation information indicating that the extended mapping data has been generated, wherein the mapping information indicates a mapping relationship between a logical block address and a physical block address and a bitmap information generator configured to receive the data generation information and generate bitmap information. The bitmap information may include information for changing a bit value corresponding to a mapping data group including the extended mapping data, among bit values included in a bitmap, to indicate the extended mapping data, and the mapping data group may include a plurality of pieces of mapping data.

A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentratedly received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold.

There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.