A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.

A method for duty cycle error detection and correction includes receiving, during a read operation performed on a memory cell, a first data strobe signal. The method also includes generating a second data strobe signal by phase delaying the first data strobe signal. The method also includes determining, based on the first data strobe signal and the second data strobe signal, whether a duty cycle corresponding to the first data strobe signal is distorted. The method also includes adjusting a clock signal based on a determination that the duty cycle is distorted.

An apparatus is described. The apparatus includes a cross-point non volatile memory cell array comprised of a first plurality of access lines and a second orthogonal plurality of access lines. Each of the first plurality of access lines are coupled to a first address decoder through a respective pass transistor. The pass transistor is coupled to control circuitry to bias the pass transistor into one of at least two states that include a first active state determined from a second address decoder and a second active state determined from the second address decoder.

According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.

According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.