A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

A processing device of a system receives a request to access a selected sector in a memory component. The selected sector is associated with a sector number. The processing device determines a virtual block corresponding to the selected sector. The virtual block is associated with a misalignment factor and a misalignment counter. The processing device determines if the misalignment counter satisfies a threshold criterion. In response to the misalignment counter satisfying the threshold criterion, the processing device generates an updated sector number by shifting the sector number by the misalignment factor and performs the access to the selected sector using the updated sector number. In response to the misalignment counter not satisfying the threshold criterion, the processing device updates the misalignment counter and performs the access to the selected sector using the sector number.

A processing device of a system receives a request to access a selected sector in a memory component. The selected sector is associated with a sector number. The processing device determines a virtual block corresponding to the selected sector. The virtual block is associated with a misalignment factor and a misalignment counter. The processing device determines if the misalignment counter satisfies a threshold criterion. In response to the misalignment counter satisfying the threshold criterion, the processing device generates an updated sector number by shifting the sector number by the misalignment factor and performs the access to the selected sector using the updated sector number. In response to the misalignment counter not satisfying the threshold criterion, the processing device updates the misalignment counter and performs the access to the selected sector using the sector number.

Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.

A semiconductor memory device, and a method of operating the semiconductor memory device, includes a memory cell array including a plurality of normal memory blocks and at least one system block, and a peripheral circuit configured to perform a program operation, a read operation, or an erase operation on the plurality of normal memory blocks or the at least one system block, wherein a data storage capacity of the at least one system block is less than a data storage capacity of each of the plurality of normal memory blocks.

Methods, systems, and devices related to techniques for saturating a host interface are described. A set of data stored at a first memory device may be communicated over an interface during a read operation performed in response to receiving a read request associated with the set of data. A control component may determine if the interface entered an idle state during portions of the read operation. Based on detecting an idle state of the interface, the control component may transfer the set of data from the first memory device to a second memory device. After receiving a second read request for the set of data, the memory device may access the set of data from the second memory device and communicate the set of data over the interface, where the interface may remain in a saturated state throughout the second read operation.

The present application provides a dual-port SRAM cell and a layout structure thereof, comprises a first and a second NMOS transistors, a first and a second PMOS transistors; the gates of the first and second NMOS transistors and the drains of the first and second PMOS transistors are connected to a word line; the source of the first NMOS transistor is connected to a first bit line; the source of the first PMOS transistor is connected to a second bit line; the source of the second NMOS transistor is connected to a third bit line; the source of the second PMOS transistor is connected to a fourth bit line; the drain of the first NMOS transistor and the gate of the first PMOS transistor are connected to a common input node of a latch.

A group control circuit includes a selection signal generation circuit and first and second activation selection circuits. The selection signal generation circuit generates a source selection signal by synchronizing an entry control signal. The first activation selection circuit generates a plurality of first activation selection signals in synchronization with a first edge clock signal. The second activation selection circuit generates a plurality of second activation selection signals in synchronization with a second edge clock signal. The first and second activation selection circuits have a parallel structure.

A semiconductor memory instance is provided that includes an array of memory cells. The array includes a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each of the semiconductor memory cells includes a floating body region configured to be charged to a level indicative of a state of the memory cell. Further includes are a plurality of buried well regions, wherein each of the buried well regions can be individually selected, and a decoder circuit to select at least one of the buried well regions.