Various embodiments of the present disclosure are directed towards a memory cell comprising a high electron affinity dielectric layer at a bottom electrode. The high electron affinity dielectric layer is one of multiple different dielectric layers vertically stacked between the bottom electrode and a top electrode overlying the bottom electrode. Further, the high electrode electron affinity dielectric layer has a highest electron affinity amongst the multiple different dielectric layers and is closest to the bottom electrode. The different dielectric layers are different in terms of material systems and/or material compositions. It has been appreciated that by arranging the high electron affinity dielectric layer closest to the bottom electrode, the likelihood of the memory cell becoming stuck during cycling is reduced at least when the memory cell is RRAM. Hence, the likelihood of a hard reset/failure bit is reduced.

A read and write circuit of a three-dimensional phase-change memory including an operation control circuit and a read and write operation circuit connected to each other. The operation control circuit is configured to load a correct operation pulse onto the read and write operation circuit. A read and write unit in the read and write operation circuit is connected to a memory cell and is configured to load the correct operation pulse onto the memory cell corresponding to the three-dimensional phase-change memory and to mirror the correct operation pulse to a mirror current. A bandgap reference source and a hysteresis comparator are connected to a mirror circuit branch. A feedback chopper circuit loop is connected across the memory cell and the mirror circuit branch and is configured to monitor a current flowing through the memory cell in real time.

An electronic device includes analog-to-digital converters each configured to receive an analog input signal and output a digital output signal corresponding to the analog input signal, an analog input signal generator configured to generate analog input signals provided to each analog-to-digital converter based on input voltages and weight data, an input signal distribution information generator configured to generate input signal distribution information indicating a distribution of the analog input signals for each of the analog-to-digital converters, an analog-to-digital converter group classifier configured to classify the analog-to-digital converters into a plurality of first analog-to-digital converter groups based on the input signal distribution information, and an analog-to-digital converter input range optimizer configured to determine an input range of each first analog-to-digital converter group based on the input signal distribution information, and each analog-to-digital converter is configured to operate according to an input range of a corresponding first analog-to-digital converter groups.

Systems, methods and apparatus to read target memory cells having an associated reference memory cell configured to be representative of drift or changes in the threshold voltages of the target memory cells. The reference cell is programmed to a predetermined threshold level when the target cells are programmed to store data. In response to a command to read the target memory cells, estimation of a drift of the threshold voltage of the reference is performed in parallel with applying an initial voltage pulse to read the target cells. Based on a result of the drift estimation, voltage pulses used to read the target cells can be modified and/or added to account for the drift estimated using the reference cell.

A semiconductor storage device capable of achieving low power and high integration is provided. A non-volatile semiconductor memory of the disclosure includes a memory cell array. The memory cell array has a NOR array with a NOR flash memory structure and a variable resistance array with a variable resistance memory structure formed on a substrate. An entry gate is formed between the NOR array and the variable resistance array. When the NOR array is accessed, the entry gate separates the variable resistance array from the NOR array.

Methods, systems, and devices for techniques for memory cells with sidewall and bulk regions in planar structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. A conductive path between the first electrode and the second electrode may extend in a direction away from a plane defined by a substrate. The self-selecting storage element may include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. The bulk region and sidewall region may extend between the first electrode and the second electrode and in the direction away from the plane defined by the substrate.

Methods, systems, and devices for techniques that support sidewall structures for memory cells in vertical structures are described. A memory cell may include a first electrode, a second electrode, and a self-selecting storage element between the first electrode and the second electrode. The self-selecting storage element may extend between the first electrode and the second electrode in a direction that is parallel with a plane defined by the substrate. The self-selecting storage element may also include a bulk region and a sidewall region. The bulk region may include a chalcogenide material having a first composition, and the sidewall region may include the chalcogenide material having a second composition that is different than the first composition. Also, the sidewall region may extend between the first electrode and the second electrode.

In-vehicle detection system includes nonvolatile memory, a controller (SoC) that reads and writes data from and in nonvolatile memory, and detector that outputs detection information to SoC. SoC changes a control signal of nonvolatile memory in accordance with the output of detector.

The method includes setting conductances for corresponding non-volatile memory (NVM) devices of a cross-bar array to zero. The method further includes determining a plurality of pulse-widths for the corresponding plurality of NVM devices based on a corresponding plurality of programming errors. Additionally, the method includes programming the NVM devices using the determined pulse-widths. Also, the method includes measuring actual conductances for the corresponding NVM devices. Further, the method includes adjusting scaling factors for the corresponding NVM devices based on the actual conductances and the corresponding programming errors. Additionally, the method includes programming the corresponding NVM devices based on the determined pulse-widths and the scaling factors.

The present disclosure relates to a synapse circuit of a neural network for performing TD-lambda temporal difference learning, the neural network approximating a value function, the synapse circuit comprising: a first resistive memory device (506); a second resistive memory device (516); and a synapse control circuit (528) configured to update a synaptic weight (g.sub.θ) of the synapse circuit by programming a resistive state of the first resistive memory device (506) based on a programmed conductance of the second resistive memory device (516).