A memory cell includes an input coupled to a read line, an output coupled to a circuit ground, a bi-polar memristor, and at least one address switch coupled to an address line to select the memory cell. A memory includes the bi-polar memristor and a one-way current conducting device, wherein the one-way current conducting device is positioned between the memristor cell output and the circuit ground, or between the read line and the memristor cell input.

In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage.

Broadly speaking, embodiments of the present techniques provide an amplification circuit comprising a sense amplifier and at least one Correlated Electron Switch (CES) configured to provide a signal to the sense amplifier. The sense amplifier outputs an amplified version of the input signal depending on the signal provided by the CES element. The signal provided by the CES element depends on the state of the CES material. The CES element provides a stable impedance to the sense amplifier, which may improve the reliability of reading data from the bit line, and reduce the number of errors introduced during the reading.

According to one embodiment of the present disclosure, a device comprises a latching circuitry, where the latching circuitry comprises at least one correlated electron random access memory (CeRAM) element. The latching circuitry further comprises a control circuit coupled to the at least one CeRAM element. The control circuit is configured to receive at least one control signal. Based on the at least one control signal, perform at least one of storing data into the latching circuitry and outputting data from the latching circuitry.

A non-volatile semiconductor memory device includes a memory array 20, including a plurality of memory elements; a selection part, selecting the memory elements of the memory array based on address data; a mode selection part 30, selecting any one of a RAM mode and a flash mode, where the RAM mode is a mode adapted to overwrite data of the memory element according to writing data, and the flash mode is a mode adapted to overwrite data of the memory element when the writing data is a first value and prohibit overwrite when the writing data is a second value; and a write control part, writing the writing data to the selected memory element according to the RAM mode or the flash mode selected by the mode selection part 30.

Disclosed are methods, systems and devices for generation of a read signal to be applied across a load for use in detecting a current impedance state of the load. In one implementation, a voltage and current of a generated read signal may be controlled so as to maintain a current impedance state of the load.

Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.

Stochastic or near-stochastic physical characteristics of resistive switching devices are utilized for generating data distinct to those resistive switching devices. The distinct data can be utilized for applications related to electronic identification. As one example, data generated from physical characteristics of resistive switching devices on a semiconductor chip can be utilized to form a distinct identifier sequence for that semiconductor chip, utilized for verification applications for communications with the semiconductor chip or utilized for generating cryptographic keys or the like for cryptographic applications.

Unclonable function circuitry includes a plurality of pairs of phase-change memory cells in a virgin state, and sensing circuitry coupled to the plurality of pairs of phase-change memory cells in the virgin state. The sensing circuitry identifies a subset of the plurality of pairs of phase-change memory cells in the virgin state based on a reliability mask. Signs of differences of effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state are sensed by the sensing circuitry. The sensing circuitry generates a string of bits based on the sensed signs of differences in the effective resistance values of the identified subset of the plurality of pairs of phase-change memory cells in the virgin state. Processing circuitry coupled to the unclonable function circuitry, in operation, executes one or more operations using the generated string of bits.

An object is to reduce the number of writes of information managed by a controller to a non-volatile memory. A controller according to one aspect of the present invention includes: a first interface unit connected to a non-volatile memory including a plurality of blocks of memory cells that enter into both a first state and a second state and in which a plurality of addresses is allocated to the plurality of blocks; an information holding unit that holds first information; and a control unit that reads first data from a first block of the non-volatile memory via the first interface unit, specifies the memory cell in the second state among the memory cells in the first block and writes second data for causing the specified memory cell in the second state to transition to the first state, and selects one of the first information and the first data on the basis of the address of the first block and writes the selected first information or first data to the first block.