Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

Various embodiments comprise devices to manage multiple memory types and reconfigure partitions in a memory device as directed by a host. In one embodiment, the apparatus is to manage commands through a first interface controller to mapped portions of a first memory not having an attribute enhanced set, and map portions of a second memory having the attribute enhanced set through a second interface controller. Additional devices are described.

Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

A data recorder for permanently storing pre-event data may include a read-write memory with a plurality of bit cells in the read-write memory. Each bit cell may have a bit state of a high value or a low value. A fusible structure in the data recorder may include a morphable element associated with each bit cell. A temperature-triggered module may thermally couple to the ambient environment and may electrically couple to each morphable element. The temperature-triggered module may be further configured to determine if a parameter of the ambient environment exceeds a predetermined threshold, and if so may then transmit a burn signal to the fusible structure so that each morphable element permanently secures the bit state for each bit cell.

Proposed as a configuration, a controlling method, and a testing method for a ferroelectric shadow memory are (1) a bit line non-precharge method, in which no precharging of a bit line is performed during a read/write operation; (2) a plate line charge share method, in which electric charge is shared between plate lines that are driven sequentially during store/recall operation; (3) a word line boost method, in which the potential on a word line is raised during a write operation; (4) a plate line driver boost method, in which the driving capacity of a plate line driver is raised during a store/recall operation; and (5) a testing method for detecting a defect in a ferroelectric capacitor by arbitrarily setting a potential on a bit line from outside a chip.

According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile semiconductor memory elements, and a controller. A wiring pattern includes a signal line that is formed between the connector and the controller and that connects the connector to the controller. On the opposite side of the controller to the signal line, the multiple nonvolatile semiconductor memory elements are aligned along the longitudinal direction of the substrate.

Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.