The present disclosure includes a mispredict recovery apparatus, which may comprise an instruction execution unit, a branch predictor, and a misprediction recovery unit (MRU). The MRU may provide discrete cycle predictions after a misprediction redirect from the instruction execution unit. The MRU may include a branch confidence filter to generate prediction confidence information for predicted branches. The MRU may include a tag content-addressable memory (CAM). The tag CAM may store frequently mispredicting low-confidence branches, probe the misprediction redirect, and obtain the prediction confidence information from the branch confidence filter. The MRU may include a mispredict recovery buffer (MRB) to store an alternate path for frequently mispredicting low-confidence branches present in the tag CAM without storing the instructions themselves. Also disclosed is a method for recovering from mispredicts associated with the instruction fetch pipeline.

The present disclosure includes a mispredict recovery apparatus, which may comprise an instruction execution unit, a branch predictor, and a misprediction recovery unit (MRU). The MRU may provide discrete cycle predictions after a misprediction redirect from the instruction execution unit. The MRU may include a branch confidence filter to generate prediction confidence information for predicted branches. The MRU may include a tag content-addressable memory (CAM). The tag CAM may store frequently mispredicting low-confidence branches, probe the misprediction redirect, and obtain the prediction confidence information from the branch confidence filter. The MRU may include a mispredict recovery buffer (MRB) to store an alternate path for frequently mispredicting low-confidence branches present in the tag CAM without storing the instructions themselves. Also disclosed is a method for recovering from mispredicts associated with the instruction fetch pipeline.

Systems, devices, and methods are provided for implementing a low power and area ternary content addressable memory (TCAM). The TCAM comprises a plurality of memristor-based TCAM (mTCAM) cells, each consisting of two memristors and two transistors. The first and second memristors are connected in series, with a first end of the first memristor connected to a first data line, first end of the second memristor connected to a second data line, and the second ends of the resistors connected together at a common node. The drain of a programming transistor is connected to the common node, with the source connected to a third data line, and the gate connected to a word line. Common node is further connected to the gate of a match-line transistor, such that if a mismatch is detected common node applies a voltage to the gate to pull-down the voltage on a pre-charged match line.

A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.

To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.

To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.

Technologies for accelerated memory lookups include a computing device having a processor and a hardware accelerator. The processor programs the accelerator with a search value, a start pointer, one or more predetermined offsets, and a record length. Each offset may be associated with a pointer type or a value type. The accelerator initializes a memory location at the start pointer and increments the memory location by the offset. The accelerator may read a pointer value from an offset, set the memory location to the pointer value, and repeat for additional offsets. The accelerator may read a value from the offset and compare the value to the search value. If the values match, the accelerator returns the address of the matching value to the processor. If the values do not match, the accelerator searches a next record based on the record length. Other embodiments are described and claimed.

A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

An apparatus (e.g., a content addressable memory system) can have a controller, a first content addressable memory coupled to the controller, and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to write data in the first content addressable memory, cause the second content addressable memory to write the data in the second content addressable memory, and cause the second content addressable memory to query the data written in the second content addressable memory while the first content addressable memory continues to write the data in the first content addressable memory.

An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.