System and method for supporting proxy based multicast forwarding in a high performance computing environment. In accordance with an embodiment, a proxy based multicast forwarding system and method can be utilized. A proxy, either software, firmware, or hardware based, can be initialized and run within a local subnet domain, wherein the proxy is a member of at least one multicast group (MCG). The proxy can be configured to forward packets to other subnet domains in several different methods.

System and method for supporting a partitioned switch forwarding table in a high performance computing environment. Described methods and systems can support partitioned switch forwarding tables (e.g., partitioned LFTs) by setting up hardware registers that divide the LFT into at least two partitions, a first partition that supports legacy forwarding (e.g., standard LID based forwarding without the need to use portions of the GRH), and a second partition to support the GRH based forwarding that is described above. In such a manner, switches and other hardware within a core fabric can behave as legacy nodes/switches having standard LFTs, while also being able to support the extended addressing supplied through the use of portions of the GRH.

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Disclosed are a method for message match table lookup, a system, a non-transitory computer-readable storage medium and a terminal. The method for message match table lookup includes: performing on-demand data bit width compression on information of a specified part of an input message; extracting N groups of data from compressed data, performing intra-group data comparison to obtain N groups of comparison results, and performing true value splicing on the N groups of comparison results, where N is an integer greater than 1; performing match searching of a ternary content addressable memory (TCAM) by using the true value splicing result as a keyword; and searching, according to a match hit result of the TCAM, for an Action Random Access Memory (Action RAM), and outputting, by the Action RAM, a table lookup request.

The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width C.sub.W and a depth C.sub.D, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

The present invention provides a power efficient content-addressable memory (CAM) architecture that is implementable on FPGAs. The provided CAM architecture comprises an array of CAM cells having a width C.sub.W and a depth C.sub.D, and being grouped into a B number of memory banks. Each of the CAM cells is configured for storing a memory bit and comprises a plurality of flip-flops configured to store at least a masking bit indicating the ternary nature of the stored memory bit and a storing bit saving the binary information of the stored memory bit. The provided CAM architecture allows activating only one bank in multiple banks irrespective of nature of the data set and is updated in a single access and saves power consumption by only accessing the memory in the activated bank. The dynamic power consumption is reduced by 40% compared with the state-of-the-art FPGA-based CAMs.

A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

In one embodiment, updating and searching of entries in a hardware content-addressable memory is coordinated to provide more searching bandwidth (e.g., for determining packet processing information), including, but not limited to, when vectors are moved among entries to free up desired entry positions for insertion of other vectors. A lookup operation is performed in content-addressable memory entries in a hardware content-addressable memory based on a lookup word to generate a content-addressable memory lookup result. Typically overlapping in time, a matching operation is performed in one or more transitory entries to generate a transitory matching result based on the lookup word. These transitory entries are populated with transitory vectors and have an associated index within the content-addressable memory, with these transitory vectors are subsequently inserted in the content-addressable memory at their associated index positions. A matching result is determined from the content-addressable memory lookup result and the transitory matching result.